Impact on Synthesis - Impact on Synthesis - 2025.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document_ID
UG1387
Release_Date
2025-12-17
Version
2025.2 English

The false path constraint is supported by synthesis and only impacts max delay (setup/recovery) path optimization. False path exceptions are recommended for portions of the design where timing can safely be ignored and for asynchronous CDC paths with no datapath delay requirements.