Introduction - Introduction - 2025.2 English - UG1137

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
UG1137
Release Date
2025-12-03
Version
2025.2 English

This document provides the software-centric information required for designing and developing system software and applications for the AMD Zynq™ UltraScale+™ MPSoCs. The Zynq UltraScale+ MPSoC family has different products, based upon the following system features:

  • Application processing unit (APU):
    • Dual or Quad-core Arm® Cortex®-A53 MPCore
    • CPU frequency up to 1.5 GHz
  • Real-time processing unit (RPU):
    • Dual-core Arm Cortex®-R5F MPCore
    • CPU frequency up to 600 MHz
  • Graphics processing unit (GPU):
    • Arm Mali-400 MP2
    • GPU frequency up to 667 MHz
  • Video codec unit (VCU):
    • Simultaneous Encode and Decode through separate cores
    • H.264 high profile level 5.2 (4Kx2K-60)
    • H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate
    • 8 and 10-bit encoding
    • 4:2:0 and 4:2:2 chroma sampling

For more details, see the Zynq UltraScale+ MPSoC Product Table and the Product Advantages.