Validate the block design. by clicking the Validate Design button in the block design diagram window.
Note: During validation, Vivado reports a critical warning that /axi_intc_0/intr is not connected. This warning can be safely ignored because v++ linker will link kernel interrupt signals to this floating intr signal.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_intc_0/intr
Create a top module wrapper for the block design.
In Source tab, right-click system.bd in Design Sources group.
Select Create HDL Wrapper….
Select Let Vivado manage wrapper and auto-update.
Click OK to generate wrapper for block design.
Generate pre-synth design
Select Generate Block Design from Flow Navigator
Select Synthesis Options to Global. It will skip IP synthesis during generation.
Click Generate. .
Generate Bitstream (Optional).
This step is optional for Vitis platforms. In most cases, a flat (non-DFX) Vitis platform does not need to generate bitstream before exporting the platform. You can execute this step after you understand its benefits and your requirements.
Generating bitstream will run through hardware design implementation for the platform. It can report errors in the early stage if your platform hardware design has potential errors that cannot be reported by the Validated Design DRC.
Here are the steps to generate bitstream:
Click Generate Bitstream in the navigation window.
Select a proper number of jobs for Launch runs on local host.
Click OK to start building.
Export the platform.
In this step, export XSA for hardware design and hardware emulation separately. These XSA files are used in step 2.
Note: Vivado 2023.2 can still export XSA with both hardware and hardware emulation info. This feature will be deprecated in the future. In most real designs, due to the complexity of the design, some peripherals cannot be emulated, or does not need to emulate at a cycle accurate level. It is a common practice to provide a simplified hardware design for hardware emulation to reduce the emulation runtime.
Click File -> Export -> Export Platform to launch the Export Hardware Platform wizard. This wizard can also be launched by Export Platform button in Flow Navigator or Platform Setup window.
Click Next in the first information page.
Select Platform Type: Hardware, click Next. If you skipped the emulation setup previously, select Hardware here.
Select Platform State: Pre-synthesis
(Optional) If you have generated bitstream in step4, enable Include bitstream, click Next.
Input Platform Properties and click Next. For example,
Name: zcu104_custom_platform
Vendor: xilinx
Board: zcu104
Version: 0.0
Description: This platform provides high PS DDR bandwidth and three clocks: 100MHz, 200MHz, and 400MHz.
Fill in XSA file name: zcu104_custom_platform_hw and keep the export directory as default.
Click Finish.
zcu104_custom_platform_hw.xsa will be generated. The export path is reported in the Tcl console.
(Optional: Only for Hardware Emulation. If you skipped the emulation setup previously, please skip the following step.)
Rerun the Export Platform wizard again and export the XSA for hardware emulation.
Note: The same hardware and hardware emulation design is used for this simple project. You can use different Vivado designs for hardware and hardware emulation. Platform developers should keep the two designs logically identical. Otherwise your emulation result cannot represent your hardware design.
Click File -> Export -> Export Platform to launch the Export Hardware Platform wizard. This wizard can also be launched by Export Platform button in Flow Navigator or Platform Setup window.
Click Next in the first information page.
Select Platform Type: Hardware Emulation, click Next.
Select Platform State: Pre-synthesis, click Next.
Input Platform Properties and click Next. For example,
Name: zcu104_custom_platform
Vendor: xilinx
Board: zcu104
Version: 0.0
Description: This platform provides high PS DDR bandwidth and three clocks: 100MHz, 200MHz, and 400MHz.
Fill in XSA file name: zcu104_custom_platform_hwemu and keep the export directory as default.
Click Finish.
zcu104_custom_platform_hwemu.xsa will be generated. The export path is reported in the Tcl console.
Alternatively, the above export can be done using Tcl scripts:
# Setting platform properties set_property platform.default_output_type "sd_card" [current_project] set_property platform.design_intent.embedded "true" [current_project] set_property platform.design_intent.server_managed "false" [current_project] set_property platform.design_intent.external_host "false" [current_project] set_property platform.design_intent.datacenter "false" [current_project] # Write pre-synthesis expandable XSA write_hw_platform -hw -force -file ./zcu104_custom_platform_hw.xsa write_hw_platform -hw_emu -force -file ./zcu104_custom_platform_hwemu.xsa