2.4. Board Setup - 2.4. Board Setup - 2025.1 English - XD347

The following figure shows how to set up the SCU35

Ensure the HSIO ADC card is fitted to the HSIO Port

Board jumper and switch settings

This is a onetime setup and the board should have been delivered to you with this default settings, but it is good to double check for the first time when you get the board.

• Make sure you connect J35 (7-8) jumper.

SPI Settings

The SPI interface from the external micro controller can be connected to the SPI ports on Click site 0

Communicating with the SCU35 Board over SPI

The application works by turning a sequence of SPI bytes into AXI Lite transaction. Throughout this transaction the SCU35 is SPI Slave.

AXI Commands are sent in the following format.

AXI 4 Lite Read

AXI Lite Write

Connection to the RPI

To connect the RPI to the SCU35 we will use the 40 Pin connector on the RPI and the click 1 position on the SCU35.

The overall connections should look as below

From the RPI we are going to use SPI0 and CS0 the pins are

This should look as in the diagrams below

This should look as in the diagram below

Setting up the RPI

As we need to use the SPI on the RPI Hat header to connect to the SCU35 Board.

The first stage is to install the spi dev libraries which can be installed using the command:

pip install spidev

The next stage is to enable the SPI port within the RPI

After doing this the RPI will need to be re booted.

Communicating between the RPI and SCU35

There is a sample script (access.py) provided under the script folder. This script, reads samples from the ADC and plot the output as shown below.

Addresses used in the system are.

• BRAM Scratch pad area 0xC000_0000

• AXI Stream Fifo 0x44A0_0000

• AXI GPIO to reset FIFO 0x4000_0000 - set lsb to 0 to reset the FIFO

Note the FIFO data content is accessed via the register address 0x44A0_0020 this reads out the data from the FIFO as received from the Zmod Scope.

Along with forming the packets this script also converts the packet data into the LSB format which the SPI IP Core expects.

Using a signal source into the Zmod scope such as a Analog Discovery will enable the signal to be captured.

Another script FFT.py will run a FFT on the captured data and plot the results.

While the final script live.py will run a live capture and plot of the data and FFT.

Data Output The script provided will read out the FIFO a number of sample from the ADC and demonstrates how to synchronize the samples.

Data is read from the address 0x44A0_0020 which is the FIFO data register, prior to reading the data samples the FIFO is Reset This reset ensure the data is read from the start of the stream

Of the 32 bits read the upper 16 relate to channel 1 and the lower relate to channel 2. Note only 14 bits are used a such the lower 2 bits can be ignored. The data is also represented as a 2’s compliment number which must be take into account plotting.

Read sequence

1. send in command to reset the RD FIFO at address 0x44A0_0018 with data 0xa5

2. send in command to reset the AXIS Stream at address 0x44A0_0028 with data 0xa5

3. send in command to read the FIFO data register at address 0x44A0_0020 - This is read a number of times as per the read Length

For information on the AXI Stream FIFO refer to the following link

https://docs.amd.com/r/en-US/pg080-axi-fifo-mm-s/Register-Space

Internal Observation

The design includes several ILA which can be accessed over the JTAG connection. The ILA is connected to the SPI I/O, Status of the Zmod IP core and the AXI networks within the FPGA, the AXI Stream output from the Zmod is also captured. A standard ILA also provides coverage of the reset of the AXI Fifo.

These ILAs are provided to help you further understand the design if desired.