Introduction - Introduction - 2025.1 English - UG997

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

Document ID
UG997
Release Date
2025-5-29
Version
2025.1 English

In this lab, you learn about generating a SAIF file after running a timing level simulation using AMD Vivado™ simulator and Questa Advanced Simulator. The lab walks you through the steps to create a SAIF file, run timing simulation, and estimate power using the SAIF data.

Note: From this lab onwards, AMD UltraScale+™ example design is used to explain the process of estimating the power through different stages, and using simulation data to enhance the accuracy of the power analysis.