In this lab, you learn about the Power Analysis and Optimization features in the AMD Vivado™ IDE. The lab walks you through the project creation and power analysis steps at the synthesis stage, using the Vivado Report Power feature in the vectorless mode. It also demonstrates using the Switching Activity Interchange Format (SAIF) file that is generated from the post-synthesis functional simulation for Vivado report power analysis.
You analyze the power of the design in Vivado IDE, and examine some of the major features in the Report Power window, and closely examine some power specific Tcl commands. You also learn how to simulate the design in the timing simulation stage using both the Vivado simulator and Questa Advanced Simulator to create a SAIF file.
You also learn how to achieve power optimization after opt_design in the Vivado IDE. Examine
the power optimization report and selectively turn power optimizations
ON or OFF on specific signals, nets, modules, or
hierarchy.