Vivado Design Suite Tutorial: Logic Simulation (UG937) - 2025.1 English - Introduces the AMD Vivado™ simulator to interactively simulate and debug AMD FPGA designs in the Vivado Integrated Design Environment (IDE). The Vivado simulator is an HDL simulator that lets you perform behavioral, functional, and timing simulations for VHDL, Verilog, and mixed-language designs. - UG937

Document ID

UG937

Release Date

2025-06-11

Version

2025.1 English