Revision History - 2025.1 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
Document ID
UG909
Release Date
2025-07-01
Version
2025.1 English

The following table shows the revision history for this document.

Section Revision Summary
07/01/2025 Version 2025.1
Create a Floorplan for the Reconfigurable Region Updated the last bullet.
Abstract Shell Design Flow Updated the topic.
Abstract Shell Creation and Usage Updated the options and figure.
Automatically Create Configuration Runs Created new topic.
Manually Create Configuration Runs Created new topic.
Supported/Unsupported Features Updated the topic.
Design Considerations and Guidelines for All AMD Devices Changed PR to DFX.
Design Elements Inside Reconfigurable Modules Updated DSP blocks.
Automatic Adjustments for PU on Pblocks Changed PR to DFX.
Design Elements Inside Reconfigurable Modules Updated the list of components.
Floorplanning for Versal Devices Added a note.
BLI Floorplan Alignment Updated the DRC error codeblock.
USER_SLL_REG Created new topic.
Floorplan Guidelines for Static Logic Created new topic.
Logical Decoupling Added a paragraph about GSR events.
Logical Decoupling at the RP Boundary Updated the section.
Using Report DFX Summary Added a paragraph and tip.
Generating the DFX Summary Report Created new topic.
Design Configuration Updated the topic.
Design Utilization Summary Updated the topic.
Design Clock Utilization Summary Updated the topic.
SLL Summary Updated the image.
PPLOC Summary Updated the image.
RP Details Updated the table and image.
Shared Tile Reason Updated the images.
Configuration Modes Updated the table and added information on AXI32.
Dynamic Function eXchange for Spartan UltraScale+ Devices Created new topics.
System Design for Configuring an FPGA Updated text in bullets.
Known Issues Updated the section for 2025.1.
Supported Devices Updated the table.