AMD has created four pieces of intellectual property specifically for use within DFX designs. There is no charge for any of these IPs, and DFX designs do not require them. They are available to assist you to quickly and easily implement key aspects of a reconfigurable design. The IPs are all found under the DFX heading within the IP catalog, and each has its own landing page on Xilinx.com with a detailed product guide.
These four IPs for DFX are available in AMD Vivado™ and can be used for any AMD device that supports DFX. These IPs now incorporate the DFX terminology in their names and throughout the IP, while remaining functionally equivalent to their Partial Reconfiguration-named predecessors. You should use the IP upgrade feature to transition any existing PR IP to DFX IP. For more information, refer to the product guides for each IP.
- DFX Controller
- The DFX Controller core provides management functions for
self-controlling partially reconfigurable designs. It is intended for enclosed
systems where all of the reconfigurable modules (RM) are known to the
controller. The optional AXI4-Lite register
interface allows the core to be reconfigured at runtime, so it can also be used
in systems where the RMs can change in the field. The core can be customized for
many Virtual Sockets, RMs per Virtual Socket, operations and interfaces. Labs 5,
6, and 7 in the
Vivado
Design Suite Tutorial: Dynamic Function eXchange (UG947) gives
examples of the DFX Controller IP in a sample design. Note: This IP is not applicable for AMD Versal™ devices.
- DFX Decoupler
- The DFX Decoupler can be used to provide a safe and managed boundary between the static logic and an RP during reconfiguration. The core can be customized for the number of interfaces, type of interfaces, decoupling functionality, status and control.
- DFX AXI Shutdown Manager
- One or more DFX AXI Shutdown Managers can be used to make the AXI interfaces between a RP and the static logic safe during reconfiguration. When active, AXI transactions sent to the RM, and AXI transactions emanating from the RM, are terminated because the RM might not be able to complete them. Failure to complete could cause system deadlock. When inactive, transactions pass unaltered.
- DFX Bitstream Monitor
- The DFX Bitstream Monitor can be used to identify partial bitstreams as they flow through the design. This information can be used for debugging or system applications such as blocking bitstream loads. Identifiers embedded at key places in partial bitstreams are extracted and reported by the core. This information can be passed to Vivado HW Debugger using an ILA core to work out what partial bitstream was fetched, if it was fetched in its entirety, and how far through the datapath it went.