I/O and Clock Planning Features - 2025.1 English - UG899

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2025-05-29
Version
2025.1 English

The following table shows the features supported for each type of project.

Table 1. I/O and Clock Planning Features
Feature I/O Planning Project RTL Design Synthesized Design Implemented Design
Read Ports from CSV and XDC Files Supported 1 N/A N/A N/A
Create or Delete Ports Supported 1 N/A N/A N/A
Read I/O Standard and Placement from XDC Files Supported 1 Supported 1 Supported 1 Supported 1
Set Part Compatibility Supported 1 Supported Supported Supported
Set Configuration Mode Supported 1 Supported Supported Supported
I/O Planning DRCs Supported 1 Supported Supported Supported
Simultaneous Switching Noise (SSN) Analysis Supported Supported Supported Supported
Clock-Aware Placement and Clock-Aware DRC N/A N/A Supported Supported
Final Sign-Off DRC N/A N/A N/A Supported
  1. The AMD Zynq™ UltraScale+™ MPSoC multiplexed I/O (MIO) pins are defined when configuring the Zynq UltraScale+ MPSoC IP. These pins are only visible in the IP configuration, the implementation IO report, or the CSV generated from an elaborated, synthesized, or implemented design.