Vivado Design Suite User Guide: I/O and Clock Planning (UG899) - 2025.1 English - Describes the I/O planning process, performing port assignments with a PCB designer in pre-RTL design, and utilizing clock resources on the target AMD FPGA with a system engineer; using the Vivado™ Design Suite to reduce internal and external wire lengths and improve system performance. - UG899

Document ID

UG899

Release Date

2025-05-29

Version

2025.1 English