X5PLL - X5PLL - 2025.1 English - Primitive: X5IO PLL - UG1727

Versal Prime Series Gen 2 Libraries Guide (UG1727)
Document ID
UG1727
Release Date
2025-05-29
Version
2025.1 English

Primitive: X5IO PLL

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
X27142-X5PLL 8pt. Roboto Text Text Text Sheet.2 XPLL X5PLL Text Line.6 CLKFB1_DESKEW CLKFB1_DESKEW Text Line.7 CLKFB2_DESKEW CLKFB2_DESKEW Text Line.8 CLKIN CLKIN Text Line.9 CLKIN1_DESKEW CLKIN1_DESKEW Text Line.25 CLKIN2_DESKEW CLKIN2_DESKEW Text Line.27 CLKOUTPHYEN CLKOUTPHYEN Text Line.29 DADDR[6:0] DADDR[6:0] Text Line.30 DI[15:0] DI[15:0] Text Line.33 PSINCDEC PSINCDEC Text Line.36 DEN DEN Text Line.37 RIU_WR_DATA[15:0] RIU_WR_DATA[15:0] Text Line.167 DWE DWE Text Line.170 PSCLK PSCLK Text Line.171 PSEN PSEN Text Line.174 PWRDWN PWRDWN Text Line.175 RIU_ADDR[7:0] RIU_ADDR[7:0] Text Line.176 RIU_CLK RIU_CLK Text Line.178 RIU_NIBBLE_SEL RIU_NIBBLE_SEL Text Line.181 RIU_WR_EN RIU_WR_EN Text Line.182 RST RST Text Line.50 DCLK DCLK Text Line.98 CLKOUTPHY CLKOUTPHY Text Line.99 CLKOUT0 CLKOUT0 Text Line.100 CLKOUT1 CLKOUT1 Text Line.101 CLKOUT2 CLKOUT2 Text Line.106 DO[15:0] DO[15:0] Text Line.107 DRDY DRDY Text Line.34 LOCKED LOCKED Text Line.35 LOCKED_FB LOCKED_FB Sheet.32 LOCKED1_DESKEW LOCKED1_DESKEW Sheet.33 LOCKED2_DESKEW LOCKED2_DESKEW Sheet.34 PSDONE PSDONE Sheet.35 RIU_RD_DATA[15:0] RIU_RD_DATA[15:0] Sheet.36 RIU_VALID RIU_VALID Text Line.43 CLKOUT3 CLKOUT3 Sheet.42 X27142-091922 X27142-091922

Introduction

The X5PLL is a mixed signal block design to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift, and duty cycle based on the same VCO frequency. The primary function of the X5PLL is to support the clocking needs of Memory Interface IP and X5IO IO Interfaces.

Port Descriptions

Port Direction Width Function
CLKFB1_DESKEW Input 1 Secondary (feedback) clock input to the PD1 block for deskewing clock network delays.
CLKFB2_DESKEW Input 1 Secondary (feedback) clock input to the PD2 block for deskewing clock network delays.
CLKIN Input 1 Primary clock input
CLKIN1_DESKEW Input 1 Primary clock input to the PD1 block for deskewing clock network delays between two different CLKOUT networks.
CLKIN2_DESKEW Input 1 Primary clock input to the PD2 block for deskewing clock network delays between two different CLKOUT networks.
CLKOUTPHY_CASC_IN_0 Input 1 X5PLL CLKOUTPHY_0 cascade input
CLKOUTPHY_CASC_IN_90 Input 1 X5PLL CLKOUTPHY_90 cascade input
CLKOUTPHY_CASC_OUT_0 Output 1 X5PLL CLKOUTPHY_0 cascade output
CLKOUTPHY_CASC_OUT_90 Output 1 X5PLL CLKOUTPHY_90 cascade output
CLKOUTPHY_0 Output 1 High-speed clock for X5IO Interfaces
CLKOUTPHY_90 Output 1 High-speed clock for X5IO Interfaces
CLKOUTPHYEN Input 1 Enable signal for CLKOUTPHY.
CLKOUT0 Output 1 CLKOUT0 output.
CLKOUT1 Output 1 CLKOUT1 output.
CLKOUT2 Output 1 CLKOUT2 output.
CLKOUT3 Output 1 CLKOUT3 output.
DADDR<6:0> Input 7 The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DCLK Input 1 The DCLK signal is the reference clock for the dynamic reconfiguration port
DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DI<15:0> Input 16 The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DO<15:0> Output 16 The dynamic reconfiguration output bus provides X5PLL data output when using dynamic reconfiguration.
DRDY Output 1 The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the X5PLLs dynamic reconfiguration feature.
DWE Input 1 The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
LOCKED Output 1 The LOCKED signal indicates that all functions requiring a LOCKED signal for the X5PLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB, LOCKED1_DESKEW, and LOCKED2_DESKEW if used.
LOCKED_FB Output 1 An output from the X5PLL that indicates when the X5PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The X5PLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The X5PLL must be reset after LOCKED is deasserted.
LOCKED1_DESKEW Output 1 Indicates if the PD1 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
LOCKED2_DESKEW Output 1 Indicates if the PD2 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
PSCLK Input 1 Phase shift clock.
PSDONE Output 1 Phase shift done.
PSEN Input 1 Phase shift enable.
PSINCDEC Input 1 Phase shift increment/decrement.
PWRDWN Input 1 Powers down instantiated but unused X5PLLs.
RIU_ADDR<7:0> Input 8 Address input for RIU.
RIU_CLK Input 1 System clock for RIU access
RIU_NIBBLE_SEL Input 1 Nibble select to enable RIU read/write.
RIU_RD_DATA<15:0> Output 16 RIU Output Read data
RIU_VALID Output 1 Indicates that last data written has been accepted when High.
RIU_WR_DATA<15:0> Input 16 RIU Input Write data
RIU_WR_EN Input 1 Enables write to RIU when High.
RST Input 1 Asynchronous reset signal. The RST signal is an asynchronous reset for the X5PLL. The X5PLL synchronously re-enables itself when this signal is released (that is, X5PLL re-enabled). A reset is required when the input clock conditions change (for example, frequency).

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
CLKFBOUT_MULT DECIMAL 4 to 43 42 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the X5LL.
CLKIN_PERIOD FLOAT(nS) 0.000 to 100.000 0.000 Specifies the input period to the CLKIN1 in ns.
CLKOUTPHY_CASCIN_EN BINARY 1'b0 to 1'b1 1'b0 X5PLL CLKOUTPHY cascade input enable
CLKOUTPHY_CASCOUT_EN BINARY 1'b0 to 1'b1 1'b0 X5PLL CLKOUTPHY cascade output enable
CLKOUT0_DIVIDE DECIMAL 2 to 128 2 Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT0_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT0 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT0_DIVIDE) / 8
CLKOUT0_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT0 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
  • 11: Interpolator is controlled by PD2.
CLKOUT1_DIVIDE DECIMAL 2 to 128 2 Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT1_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT1 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT1_DIVIDE) / 8
CLKOUT1_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT0 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
  • 11: Interpolator is controlled by PD2.
CLKOUT2_DIVIDE DECIMAL 2 to 128 2 Specifies the amount to divide the CLKOUT2 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT2_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT2 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT2_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT2 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT2_DIVIDE) / 8
CLKOUT2_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT2 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
  • 11: Interpolator is controlled by PD2.
CLKOUT3_DIVIDE DECIMAL 2 to 128 2 Specifies the amount to divide the CLKOUT3 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT3_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT3 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT3_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT3 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT3_DIVIDE) / 8
CLKOUT3_PHASE_CTRL BINARY 2'b00 to 2'b11 2'b00 CLKOUT3 counter variable fine phase shift or deskew select.
  • 00: Interpolator is not controlled by either deskew or phase shift interface.
  • 01: Interpolator is controlled by Deskew.
  • 10: Interpolator is controlled by phase shift interface.
  • 11: Interpolator is controlled by PD2.
DESKEW_DELAY_EN1 STRING "FALSE", "TRUE" "FALSE" Set to TRUE to enable the optional programmable delay in the PD1 circuit.
DESKEW_DELAY_EN2 STRING "FALSE", "TRUE" "FALSE" Set to TRUE to enable the optional programmable delay in the PD2 circuit.
DESKEW_DELAY_PATH1 STRING "FALSE", "TRUE" "FALSE" Determines if the CLKIN1_DESKEW path or the CLKFB1_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB1_DESKEW, FALSE = CLKIN1_DESKEW.
DESKEW_DELAY_PATH2 STRING "FALSE", "TRUE" "FALSE" Determines if the CLKIN2_DESKEW path or the CLKFB2_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB2_DESKEW, FALSE = CLKIN2_DESKEW.
DESKEW_DELAY1 DECIMAL 0 to 63 0 Value of the optional programmable delay in the PD1 circuit.
DESKEW_DELAY2 DECIMAL 0 to 63 0 Value of the optional programmable delay in the PD2 circuit.
DESKEW_MUXIN_SEL BINARY 1'b0 to 1'b1 1'b0 Deskew mux selection
DESKEW2_MUXIN_SEL BINARY 1'b0 to 1'b1 1'b0 Deskew mux selection
DIVCLK_DIVIDE DECIMAL 1 to 12 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
IS_CLKFB1_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFB1_DESKEW pin.
IS_CLKFB2_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFB2_DESKEW pin.
IS_CLKIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN pin.
IS_CLKIN1_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN1_DESKEW pin.
IS_CLKIN2_DESKEW_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN2_DESKEW pin.
IS_PSEN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PSEN pin.
IS_PSINCDEC_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PSINCDEC pin.
IS_PWRDWN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin.
LOCK_WAIT STRING "FALSE", "TRUE" "FALSE" Wait during the configuration for the startup for the X5PLL to lock.
REF_JITTER 3 significant digit FLOAT 0.000 to 0.200 0.010 Allows specification of the expected jitter on CLKIN to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the unit interval (UI) (the maximum peak to peak value) of the expected jitter on the input clock.
SIM_ADJ_CLK0_CASCADE STRING "FALSE", "TRUE" "FALSE"
XPLL_CONNECT_TO_NOCMC STRING "NONE", "DDR", "LP4" "NONE" Indicates if the X5PLL is used to drive the DDRMC.