OBUF_ODDR - OBUF_ODDR - 2025.1 English - Primitive: Output Buffer with ODDR MUX - UG1727

Versal Prime Series Gen 2 Libraries Guide (UG1727)

Document ID
UG1727
Release Date
2025-05-29
Version
2025.1 English

Primitive: Output Buffer with ODDR MUX

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
X27137-OBUF_ODDR Sheet.1 OBUF OBUF_ODDR Dynamic connector path37-1 path39-6 Dynamic connector.5 path44-5 path46-9 path85 path87 text89 I_0 I_0 path85-1 path87-8 text89-0 I_1 I_1 text89-0-6 C C path716 Buffer.6 Sheet.17 O path3621 path3623 O Sheet.20 Sheet.21 Sheet.22 path3646 path3648 Sheet.25 path3653 path3655 Sheet.28 Output to device pad Output to device pad Sheet.29 X27137-091922 X27137-091922

Introduction

The OBUF_ODDR is an output buffer that provides the unregistered ODDR MUX. I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
C Input 1 Clock controlled ODDR MUX select
I_0 Input 1 Parallel data input 0
I_1 Input 1 Parallel data input 1
O Output 1 Output of OBUF to be connected directly to top-level output port.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUF_ODDR: Output Buffer with ODDR MUX
--            Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

OBUF_ODDR_inst : OBUF_ODDR
port map (
   O => O,     -- 1-bit output: Buffer output (connect directly to top-level port)
   C => C,     -- 1-bit input: Clock controlled ODDR MUX select
   I_0 => I_0, -- 1-bit input: Parallel data input 0
   I_1 => I_1  -- 1-bit input: Parallel data input 1
);

-- End of OBUF_ODDR_inst instantiation

Verilog Instantiation Template


// OBUF_ODDR: Output Buffer with ODDR MUX
//            Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

OBUF_ODDR OBUF_ODDR_inst (
   .O(O),     // 1-bit output: Buffer output (connect directly to top-level port)
   .C(C),     // 1-bit input: Clock controlled ODDR MUX select
   .I_0(I_0), // 1-bit input: Parallel data input 0
   .I_1(I_1)  // 1-bit input: Parallel data input 1
);

// End of OBUF_ODDR_inst instantiation