Primitive: 3-State Output Buffer with ODDR MUX
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
Introduction
The OBUFT_ODDR is a 3-state output buffer that provides the unregistered ODDR MUX. The OBUFT_ODDR implements 3-state outputs or bidirectional I/O.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| C | Input | 1 | Clock controlled ODDR MUX select |
| I_0 | Input | 1 | Parallel data input 0 |
| I_1 | Input | 1 | Parallel data input 1 |
| O | Output | 1 | Output of OBUF to be connected directly to top-level output port. |
| T | Input | 1 | 3-state enable input. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFT_ODDR: 3-State Output Buffer with ODDR MUX
-- Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1
OBUFT_ODDR_inst : OBUFT_ODDR
port map (
O => O, -- 1-bit output: Buffer output (connect directly to top-level port)
C => C, -- 1-bit input: Clock controlled ODDR MUX select
I_0 => I_0, -- 1-bit input: Parallel data input 0
I_1 => I_1, -- 1-bit input: Parallel data input 1
T => T -- 1-bit input: 3-state enable input
);
-- End of OBUFT_ODDR_inst instantiation
Verilog Instantiation Template
// OBUFT_ODDR: 3-State Output Buffer with ODDR MUX
// Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1
OBUFT_ODDR OBUFT_ODDR_inst (
.O(O), // 1-bit output: Buffer output (connect directly to top-level port)
.C(C), // 1-bit input: Clock controlled ODDR MUX select
.I_0(I_0), // 1-bit input: Parallel data input 0
.I_1(I_1), // 1-bit input: Parallel data input 1
.T(T) // 1-bit input: 3-state enable input
);
// End of OBUFT_ODDR_inst instantiation