OBUFTDS_ODDR - OBUFTDS_ODDR - 2025.1 English - Primitive: Differential 3-state Output Buffer with ODDR MUX

Primitive: Differential 3-state Output Buffer with ODDR MUX

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: OUTPUT_BUFFER

Introduction

The OBUFTDS_ODDR is a differential 3-state output buffer primitive that provides the unregistered ODDR MUX.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port	Direction	Width	Function
C	Input	1	Clock controlled ODDR MUX select
I_0	Input	1	Parallel data input 0
I_1	Input	1	Parallel data input 1
O	Output	1	Diff_p output. Connect directly to a top-level port in the design.
OB	Output	1	Diff_n output. Connect directly to a top-level port in the design.
T	Input	1	3-state enable input.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- OBUFTDS_ODDR: Differential 3-state Output Buffer with ODDR MUX
--               Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

OBUFTDS_ODDR_inst : OBUFTDS_ODDR
port map (
   O => O,     -- 1-bit output: Diff_p output (connect directly to top-level port)
   OB => OB,   -- 1-bit output: Diff_n output (connect directly to top-level port)
   C => C,     -- 1-bit input: Clock controlled ODDR MUX select
   I_0 => I_0, -- 1-bit input: Parallel data input 0
   I_1 => I_1, -- 1-bit input: Parallel data input 1
   T => T      -- 1-bit input: 3-state enable input
);

-- End of OBUFTDS_ODDR_inst instantiation

Verilog Instantiation Template


// OBUFTDS_ODDR: Differential 3-state Output Buffer with ODDR MUX
//               Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

OBUFTDS_ODDR OBUFTDS_ODDR_inst (
   .O(O),     // 1-bit output: Diff_p output (connect directly to top-level port)
   .OB(OB),   // 1-bit output: Diff_n output (connect directly to top-level port)
   .C(C),     // 1-bit input: Clock controlled ODDR MUX select
   .I_0(I_0), // 1-bit input: Parallel data input 0
   .I_1(I_1), // 1-bit input: Parallel data input 1
   .T(T)      // 1-bit input: 3-state enable input
);

// End of OBUFTDS_ODDR_inst instantiation