IOBUF_ODDR - IOBUF_ODDR - 2025.1 English - Primitive: Input/Output Buffer with ODDR MUX

Primitive: Input/Output Buffer with ODDR MUX

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUF_ODDR primitive is needed when bidirectional signals require both an input buffer and a 3-state output buffer with an active-High 3-state T pin. The IOBUF_ODDR provides the unregistered ODDR MUX. A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled.

I/O attributes that do not impact the logic function of the component such as IOSTANDARD, DRIVE and SLEW should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port	Direction	Width	Function
C	Input	1	Clock controlled ODDR MUX select
DCITERMDISABLE	Input	1	Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I_0	Input	1	Parallel data input 0
I_1	Input	1	Parallel data input 1
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
IO	Inout	1	Bidirectional port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
OSC<3:0>	Input	4	Offset cancellation value
OSC_EN	Input	1	Offset cancellation enable
T	Input	1	3-state enable input signifying whether the buffer acts as an input or output.
VREF	Input	1	Vref input

Design Entry Method

Instantiation	Yes
Inference	Recommended
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
SIM_INPUT_BUFFER_OFFSET	DECIMAL	-50 to 50	0	Offset value for simulation purposes.
USE_IBUFDISABLE	STRING	"FALSE", "T_CONTROL", "TRUE"	"FALSE"	Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUF_ODDR: Input/Output Buffer with ODDR MUX
--             Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

IOBUF_ODDR_inst : IOBUF_ODDR
generic map (
   SIM_INPUT_BUFFER_OFFSET => 0, -- Offset value for simulation (-50-50)
   USE_IBUFDISABLE => "FALSE"    -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
   O => O,                           -- 1-bit output: Buffer output
   C => C,                           -- 1-bit input: Clock controlled ODDR MUX select
   DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
   IBUFDISABLE => IBUFDISABLE,       -- 1-bit input: Buffer disable input, high=disable
   IO => IO,                         -- 1-bit inout: Buffer inout (connect directly to top-level port)
   I_0 => I_0,                       -- 1-bit input: Parallel data input 0
   I_1 => I_1,                       -- 1-bit input: Parallel data input 1
   OSC => OSC,                       -- 4-bit input: Offset cancellation value
   OSC_EN => OSC_EN,                 -- 1-bit input: Offset cancellation enable
   T => T,                           -- 1-bit input: 3-state enable input
   VREF => VREF                      -- 1-bit input: Vref input
);

-- End of IOBUF_ODDR_inst instantiation

Verilog Instantiation Template


// IOBUF_ODDR: Input/Output Buffer with ODDR MUX
//             Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

IOBUF_ODDR #(
   .SIM_INPUT_BUFFER_OFFSET(0), // Offset value for simulation (-50-50)
   .USE_IBUFDISABLE("FALSE")    // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IOBUF_ODDR_inst (
   .O(O),                           // 1-bit output: Buffer output
   .C(C),                           // 1-bit input: Clock controlled ODDR MUX select
   .DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
   .IBUFDISABLE(IBUFDISABLE),       // 1-bit input: Buffer disable input, high=disable
   .IO(IO),                         // 1-bit inout: Buffer inout (connect directly to top-level port)
   .I_0(I_0),                       // 1-bit input: Parallel data input 0
   .I_1(I_1),                       // 1-bit input: Parallel data input 1
   .OSC(OSC),                       // 4-bit input: Offset cancellation value
   .OSC_EN(OSC_EN),                 // 1-bit input: Offset cancellation enable
   .T(T),                           // 1-bit input: 3-state enable input
   .VREF(VREF)                      // 1-bit input: Vref input
);

// End of IOBUF_ODDR_inst instantiation