IOBUFDS_INTERMDISABLE_ODDR - IOBUFDS_INTERMDISABLE_ODDR - 2025.1 English - Primitive: Differential Bidirectional Buffer with Input Buffer Disable, On-die Input and ODDR MUX

Primitive: Differential Bidirectional Buffer with Input Buffer Disable, On-die Input and ODDR MUX

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUFDS_INTERMDISABLE_ODDR primitive is available in the X5IO I/O banks and provides the unregistered ODDR MUX. It has an IBUFDISABLE port that can be used to disable the input buffer during periods when the buffer is not being used. The IOBUFDS_INTERMDISABLE_ODDR primitive also has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature.

The IOBUFDS_INTERMDISABLE_ODDR primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High and the output buffer is 3-stated (T = High). The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. If the I/O is using the on-die receiver termination feature, this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High and the output buffer is 3-stated. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination are controlled by IBUFDISABLE and INTERMDISABLE, respectively. When the output buffer is not 3-stated (T = Low), the input buffer and on-die receiver termination are disabled and the O output (to the internal logic) is forced to a logic-Low. These features can be combined to reduce power whenever the input is idle for a period of time.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port	Direction	Width	Function
C	Input	1	Clock controlled ODDR MUX select
I_0	Input	1	Parallel data input 0
I_1	Input	1	Parallel data input 1
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
INTERMDISABLE	Input	1	Control to enable/disable on-chip input termination. This is generally used to reduce power in long periods of an idle state.
IO	Inout	1	Bidirectional diff_p port to be connected directly to top-level inout port.
IOB	Inout	1	Bidirectional diff_n port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
T	Input	1	3-state enable input signifying whether the buffer acts as an input or output.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDS_INTERMDISABLE_ODDR: Differential Bidirectional Buffer with Input Buffer Disable, On-die Input and ODDR MUX
--                             Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

IOBUFDS_INTERMDISABLE_ODDR_inst : IOBUFDS_INTERMDISABLE_ODDR
generic map (
   USE_IBUFDISABLE => "TRUE"  -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE)
)
port map (
   O => O,                         -- 1-bit output: Buffer output
   C => C,                         -- 1-bit input: Clock controlled ODDR MUX select
   IBUFDISABLE => IBUFDISABLE,     -- 1-bit input: Buffer disable input, high=disable
   INTERMDISABLE => INTERMDISABLE, -- 1-bit input: Input Termination Disable
   IO => IO,                       -- 1-bit inout: Diff_p inout (connect directly to top-level port)
   IOB => IOB,                     -- 1-bit inout: Diff_n inout (connect directly to top-level port)
   I_0 => I_0,                     -- 1-bit input: Parallel data input 0
   I_1 => I_1,                     -- 1-bit input: Parallel data input 1
   T => T                          -- 1-bit input: 3-state enable input
);

-- End of IOBUFDS_INTERMDISABLE_ODDR_inst instantiation

Verilog Instantiation Template


// IOBUFDS_INTERMDISABLE_ODDR: Differential Bidirectional Buffer with Input Buffer Disable, On-die Input and ODDR MUX
//                             Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

IOBUFDS_INTERMDISABLE_ODDR #(
   .USE_IBUFDISABLE("TRUE")  // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE)
)
IOBUFDS_INTERMDISABLE_ODDR_inst (
   .O(O),                         // 1-bit output: Buffer output
   .C(C),                         // 1-bit input: Clock controlled ODDR MUX select
   .IBUFDISABLE(IBUFDISABLE),     // 1-bit input: Buffer disable input, high=disable
   .INTERMDISABLE(INTERMDISABLE), // 1-bit input: Input Termination Disable
   .IO(IO),                       // 1-bit inout: Diff_p inout (connect directly to top-level port)
   .IOB(IOB),                     // 1-bit inout: Diff_n inout (connect directly to top-level port)
   .I_0(I_0),                     // 1-bit input: Parallel data input 0
   .I_1(I_1),                     // 1-bit input: Parallel data input 1
   .T(T)                          // 1-bit input: 3-state enable input
);

// End of IOBUFDS_INTERMDISABLE_ODDR_inst instantiation