Primitive: Differential Input/Output Buffer Primitive with Complementary Outputs for the Input Buffer and ODDR MUX
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Introduction
The IOBUFDS_DIFF_OUT_ODDR is a differential input/output buffer primitive with complementary outputs (O and OB) that provides the unregistered ODDR MUX. A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled. TM and TS must be connected to the same input from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| C | Input | 1 | Clock controlled ODDR MUX select |
| I_0 | Input | 1 | Parallel data input 0 |
| I_1 | Input | 1 | Parallel data input 1 |
| IO | Inout | 1 | Bidirectional diff_p port to be connected directly to top-level inout port. |
| IOB | Inout | 1 | Bidirectional diff_n port to be connected directly to top-level inout port. |
| O | Output | 1 | Output path of the buffer. |
| OB | Output | 1 | Output path of the buffer. |
| TM | Input | 1 | 3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input. |
| TS | Input | 1 | 3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFDS_DIFF_OUT_ODDR: Differential Input/Output Buffer Primitive with Complementary Outputs for the Input Buffer and ODDR MUX
-- Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1
IOBUFDS_DIFF_OUT_ODDR_inst : IOBUFDS_DIFF_OUT_ODDR
port map (
O => O, -- 1-bit output: Buffer diff_p output
OB => OB, -- 1-bit output: Buffer diff_n output
C => C, -- 1-bit input: Clock controlled ODDR MUX select
IO => IO, -- 1-bit inout: Diff_p inout (connect directly to top-level port)
IOB => IOB, -- 1-bit inout: Diff_n inout (connect directly to top-level port)
I_0 => I_0, -- 1-bit input: Parallel data input 0
I_1 => I_1, -- 1-bit input: Parallel data input 1
TM => TM, -- 1-bit input: 3-state master enable input
TS => TS -- 1-bit input: 3-state slave enable input
);
-- End of IOBUFDS_DIFF_OUT_ODDR_inst instantiation
Verilog Instantiation Template
// IOBUFDS_DIFF_OUT_ODDR: Differential Input/Output Buffer Primitive with Complementary Outputs for the Input Buffer and ODDR MUX
// Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1
IOBUFDS_DIFF_OUT_ODDR IOBUFDS_DIFF_OUT_ODDR_inst (
.O(O), // 1-bit output: Buffer diff_p output
.OB(OB), // 1-bit output: Buffer diff_n output
.C(C), // 1-bit input: Clock controlled ODDR MUX select
.IO(IO), // 1-bit inout: Diff_p inout (connect directly to top-level port)
.IOB(IOB), // 1-bit inout: Diff_n inout (connect directly to top-level port)
.I_0(I_0), // 1-bit input: Parallel data input 0
.I_1(I_1), // 1-bit input: Parallel data input 1
.TM(TM), // 1-bit input: 3-state master enable input
.TS(TS) // 1-bit input: 3-state slave enable input
);
// End of IOBUFDS_DIFF_OUT_ODDR_inst instantiation