IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR - IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR - 2025.1 English - Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable, On-die Input Termination Disable and ODDR MUX

Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable, On-die Input Termination Disable and ODDR MUX

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR primitive is available in the X5IO I/O banks and provides the unregistered ODDR MUX. The IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR primitive has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature. TM and TS must be connected to the same input (T) from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.

The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for the IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR primitive to have the expected behavior that is specific to the architecture. If the I/O is using the on-die receiver termination features, this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High and the output buffer is 3-stated. When the output buffer is 3-stated (T = High), any on-die receiver termination is controlled by INTERMDISABLE. When the output buffer is not 3-stated (T = Low), the input buffer and on-die receiver termination are disabled and the O output (to the internal logic) is forced to a logic-Low.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port	Direction	Width	Function
C	Input	1	Clock controlled ODDR MUX select
I_0	Input	1	Parallel data input 0
I_1	Input	1	Parallel data input 1
IBUFDISABLE	Input	1	The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'.
INTERMDISABLE	Input	1	Control to enable/disable on-chip input termination. This is generally used to reduce power in long periods of an idle state.
IO	Inout	1	Bidirectional diff_p port to be connected directly to top-level inout port.
IOB	Inout	1	Bidirectional diff_n port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
OB	Output	1	Output path of the buffer.
TM	Input	1	3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input.
TS	Input	1	3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input.

Design Entry Method

Instantiation	Recommended
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	This attribute must be unspecified or set to "TRUE" if specified.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable, On-die Input Termination Disable and ODDR MUX
--                                      Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR_inst : IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR
port map (
   O => O,                         -- 1-bit output: Buffer diff_p output
   OB => OB,                       -- 1-bit output: Buffer diff_n output
   C => C,                         -- 1-bit input: Clock controlled ODDR MUX select
   IBUFDISABLE => IBUFDISABLE,     -- 1-bit input: Must be tied to a logic '0'
   INTERMDISABLE => INTERMDISABLE, -- 1-bit input: Input Termination Disable
   IO => IO,                       -- 1-bit inout: Diff_p inout (connect directly to top-level port)
   IOB => IOB,                     -- 1-bit inout: Diff_n inout (connect directly to top-level port)
   I_0 => I_0,                     -- 1-bit input: Parallel data input 0
   I_1 => I_1,                     -- 1-bit input: Parallel data input 1
   TM => TM,                       -- 1-bit input: 3-state master enable input
   TS => TS                        -- 1-bit input: 3-state slave enable input
);

-- End of IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable, On-die Input Termination Disable and ODDR MUX
//                                      Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR_inst (
   .O(O),                         // 1-bit output: Buffer diff_p output
   .OB(OB),                       // 1-bit output: Buffer diff_n output
   .C(C),                         // 1-bit input: Clock controlled ODDR MUX select
   .IBUFDISABLE(IBUFDISABLE),     // 1-bit input: Must be tied to a logic '0'
   .INTERMDISABLE(INTERMDISABLE), // 1-bit input: Input Termination Disable
   .IO(IO),                       // 1-bit inout: Diff_p inout (connect directly to top-level port)
   .IOB(IOB),                     // 1-bit inout: Diff_n inout (connect directly to top-level port)
   .I_0(I_0),                     // 1-bit input: Parallel data input 0
   .I_1(I_1),                     // 1-bit input: Parallel data input 1
   .TM(TM),                       // 1-bit input: 3-state master enable input
   .TS(TS)                        // 1-bit input: 3-state slave enable input
);

// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_ODDR_inst instantiation