IOBUFDSE3_ODDR - IOBUFDSE3_ODDR - 2025.1 English - Primitive: Differential Bidirectional I/O Buffer with Offset Calibration and ODDR MUX

Primitive: Differential Bidirectional I/O Buffer with Offset Calibration and ODDR MUX

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The differential bidirectional input/output buffer primitive (IOBUFDSE3_ODDR) is only available in X5IO I/O banks and provides the unregistered ODDR MUX. This primitive has functions similar to the IOBUFDS_DCIEN along with controls for offset calibration with input buffer disable control (IBUFDISABLE) and on-die input termination disable control (DCITERMDISABLE) for the input buffer. The offset calibration feature is accessed using the OSC_EN[1:0] and OSC[3:0] ports. The V_REF scan feature is not supported with this primitive.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, IBUF_LOW_PWR, and SLEW, should be supplied in XDC or to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912). Attributes that impact the functionality, such as SIM_INPUT_BUFFER_OFFSET, must be supplied to the component via a generic_map (VHDL) or parameter (Verilog) to have the correct simulation behavior.

Port Descriptions

Port	Direction	Width	Function
C	Input	1	Clock controlled ODDR MUX select
DCITERMDISABLE	Input	1	Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I_0	Input	1	Parallel data input 0
I_1	Input	1	Parallel data input 1
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
IO	Inout	1	Bidirectional diff_p port to be connected directly to top-level inout port.
IOB	Inout	1	Bidirectional diff_n port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
OSC<3:0>	Input	4	Offset cancellation value
OSC_EN<1:0>	Input	2	Offset cancellation enable
T	Input	1	3-state enable input signifying whether the buffer acts as an input or output.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
SIM_DEVICE	STRING	"VERSAL_PRIME2_RF"	""	Set the device version for simulation functionality.
SIM_INPUT_BUFFER_OFFSET	DECIMAL	-50 to 50	0	Offset value for simulation purposes.
USE_IBUFDISABLE	STRING	"FALSE", "T_CONTROL", "TRUE"	"FALSE"	Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDSE3_ODDR: Differential Bidirectional I/O Buffer with Offset Calibration and ODDR MUX
--                 Versal Prime Series Gen 2
-- Xilinx HDL Language Template, version 2025.1

IOBUFDSE3_ODDR_inst : IOBUFDSE3_ODDR
generic map (
   SIM_DEVICE => "VERSAL_PRIME2",  -- Set the device version for simulation functionality (VERSAL_PRIME2)
   SIM_INPUT_BUFFER_OFFSET => 0, -- Offset value for simulation (-50-50)
   USE_IBUFDISABLE => "FALSE"    -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
   O => O,                           -- 1-bit output: Buffer output
   C => C,                           -- 1-bit input: Clock controlled ODDR MUX select
   DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
   IBUFDISABLE => IBUFDISABLE,       -- 1-bit input: Buffer disable input, high=disable
   IO => IO,                         -- 1-bit inout: Diff_p inout (connect directly to top-level port)
   IOB => IOB,                       -- 1-bit inout: Diff_n inout (connect directly to top-level port)
   I_0 => I_0,                       -- 1-bit input: Parallel data input 0
   I_1 => I_1,                       -- 1-bit input: Parallel data input 1
   OSC => OSC,                       -- 4-bit input: Offset cancellation value
   OSC_EN => OSC_EN,                 -- 2-bit input: Offset cancellation enable
   T => T                            -- 1-bit input: 3-state enable input
);

-- End of IOBUFDSE3_ODDR_inst instantiation

Verilog Instantiation Template


// IOBUFDSE3_ODDR: Differential Bidirectional I/O Buffer with Offset Calibration and ODDR MUX
//                 Versal Prime Series Gen 2
// Xilinx HDL Language Template, version 2025.1

IOBUFDSE3_ODDR #(
   .SIM_DEVICE("VERSAL_PRIME2"),  // Set the device version for simulation functionality (VERSAL_PRIME2)
   .SIM_INPUT_BUFFER_OFFSET(0), // Offset value for simulation (-50-50)
   .USE_IBUFDISABLE("FALSE")    // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IOBUFDSE3_ODDR_inst (
   .O(O),                           // 1-bit output: Buffer output
   .C(C),                           // 1-bit input: Clock controlled ODDR MUX select
   .DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
   .IBUFDISABLE(IBUFDISABLE),       // 1-bit input: Buffer disable input, high=disable
   .IO(IO),                         // 1-bit inout: Diff_p inout (connect directly to top-level port)
   .IOB(IOB),                       // 1-bit inout: Diff_n inout (connect directly to top-level port)
   .I_0(I_0),                       // 1-bit input: Parallel data input 0
   .I_1(I_1),                       // 1-bit input: Parallel data input 1
   .OSC(OSC),                       // 4-bit input: Offset cancellation value
   .OSC_EN(OSC_EN),                 // 2-bit input: Offset cancellation enable
   .T(T)                            // 1-bit input: 3-state enable input
);

// End of IOBUFDSE3_ODDR_inst instantiation