DDRMC5E - DDRMC5E - 2025.1 English - Primitive: DDR5 memory controller - UG1727

Versal Prime Series Gen 2 Libraries Guide (UG1727)

Document ID
UG1727
Release Date
2025-05-29
Version
2025.1 English

Primitive: DDR5 memory controller

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: BUFFER

Introduction

The DDRMC5E is the DDR5 memory controller Register Interface Unit block in Versal devices. This element is not intended to be instantiated, used, or modified outside of AMD-generated IP.