The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 07/16/2025 Version 2025.1 | |
| General Updates | Editorial and link revisions. |
| Platform Support for Segmented Configuration Flow | Added new topic. |
| Special Considerations for Embedded Platform Creation | Hidden topic as contents need to be reworked for 2025.2. |
| 05/29/2025 Version 2025.1 | |
| Adding Hardware Interfaces | Updated AXI4-Stream Interfaces platform properties and added example. |
| AI Engine Event Trace in Hardware | Revised AI Engine events to add AI Engine metrics and added descriptions regarding AI Engine-ML and AI Engine-ML Gen2 events. |
| AI Engine Partitions and Runtime Control and Reload | New topic on reset and reload of AI Engine partitions when running design on HW. |
| Building and Running the System | Added steps for choosing pre-built base platform or custom platform. |
| Functional Simulation and Verification in Vitis | New topic covering AIE graph and HLS kernel functional verification in Python or the MATLAB® environment. |
| Hardware Emulation and Hardware Run Profiling | Added new metrics start_to_bytes_transferred and interface_tile_latency. |
| Incremental Design Management | Added scenario for modifying Vitis Subsystem components. |
| Integrating the System | Updated keywords. |
| Interpreting Data in the Waveform Views | Removed deprecated reference to OpenCL. |
| Linking a VSS Component | Added description and more examples for hierarchical Vitis Subsystem. |
| Mapping Kernel Ports to Memory | Updated link to tutorial. |
| NoC Memory Configuration | New topic describing how Vitis can access NoC Memory configurations for DDR and LPDDR memories in the platform, and considerations for GMIO access to these memories. |
| Packaging the RTL Code as a Vitis XO | Added note clarifying that XRT controlled RTL IP requires packaged XO for kernel information. |
| Pre-built Base Platforms | Updated platform versions to 2025.1 and added VEK385 example. |
| SSI Technology Devices and Hardware Platforms | New topic on how to set up a Vivado platform that supports an SSI technology based device. |
| Running Traffic Generators in Python/C++ | Removed deprecated reference to sw_emu. Clarified example for Python API. |
| Simulator Support in Hardware Emulation | Updated tool versions in examples. |
| Special Considerations for Embedded Platform Creation | New topic on recommendations for placing logic in platform versus kernel. |
| Specifying SLR Region for SSI Devices | New topic on specifying a SLR region through a property for SSI devices. |
| Using Traffic Generators for AI Engine Designs | Removed deprecated reference to sw_emu. |
| Using Traffic Generators in AI Engine Graphs | Removed deprecated reference to sw_emu. |
| VARRAY Supported Data Types | New topic on data type object used by tools such as Vitis functional simulation. |
| VFS Objects | New topic on Vitis functional simulation objects. |
| Vitis Functional Simulation Overview | New topic with content for Vitis functional simulation. |
| Vitis Key Concepts | Added Vitis subsystem and Vitis functional simulation terminology. |
| Vitis Subsystem Flow | New topic describing the Vitis subsystem. |