In the AMD Vitis™ development flow, RTL IP from the Vivado Design Suite can be packaged as compiled AMD object (.xo) files) that can be linked into a device binary (.xclbin), as long as they adhere to Vivado IP packaging guidelines, and requirements of the Vitis compiler for linking the system.
RTL kernels can be user-managed kernels that do not meet XRT
requirements for execution control, but rather implement any number of possible control
schemes specified by existing RTL designs. Alternatively, RTL kernels can adhere to the
requirements of the ap_ctrl_chain or ap_ctrl_hs control protocols needed for XRT-managed
kernels.
The following sections describe the kernel interface requirements for the Vitis compiler to link kernels into a system. These requirements are common to software controllable and non-software controlled kernels. The control requirements for XRT-managed kernels are also described, in addition to any additional requirements. Finally, the development flow is described to help you package the RTL IP in theVivado Design Suite as RTL kernels for use in the Vitis environment.
To be integrated into the Vitis tool flow, an RTL module must minimally meet the requirements in RTL Kernel Interface Requirements. The need to meet the kernel interface requirements applies to both XRT-managed and user-managed kernels.
In addition, XRT-managed kernels must satisfy the requirements described in Control Requirements for XRT-Managed Kernels to be executed and profiled by XRT. RTL kernels support the hardware emulation and the hardware flows.
User-managed kernels must have the signal interfaces needed by the Vitis compiler to allow it to link the kernels to other kernels and to the target platform, but do not need to adhere to the strict execution protocol of XRT. In this way, existing RTL IP can be more rapidly and simply integrated into the Vitis environment.
Revise your RTL module to meet the kernel requirements outlined in the following sections.