NoC Memory Configuration - 2025.1 English - UG1701

The extensible platform built in Vivado as described in Platform Creation Basics provides a comprehensive system for processing system (PS), network-on-chip (NoC), memory controllers, clock sources, other IPs and RTL modules tailored to specific system requirements. The NoC memory configuration, a crucial aspect of this platform, allows access to DDR /LPDDR memories available on the device. Understanding this configuration is paramount for optimizing memory usage and maximizing performance. For more details on the NoC memory configuration, see Configuring the Memory Controller in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) .

NoC Memory Configuration in Vivado

The hierarchical approach to NoC memory configuration enables the accessibility of multiple DDR/LPPDDR memories within a platform. An example showcasing this approach is an IP integrator design in Vivado that features four NoC IPs with integrated memory controllers (NoC_C0_C1, NoC_C2, NoC_C3 and NoC_C4). These memory controller NoC IPs are further connected to an aggregate NoC (aggr_noc) IP. This configuration effectively distributes memory access across multiple NoC IPs, enhancing system efficiency.

Figure 1. Memory Hierarchy in IPI Design

Each of the four memory controller NoC IPs have platform attributes with unique tags set on them, enabling individual access to assigned LPPDR memories For example, NoC_C2 has LPDDR2 sptag allowing exclusive access to its associated memory.

Similarly, the aggregate NoC IP aggr_nochas its own unique tag that grants flexibility to access all four LPPDR memories, offering extensive memory utilization as per the application requirements.

This hierarchical memory structure facilitates access to the entire memory space within the platform through the aggregate NoC or individual memory access based on specific needs. This approach enhances memory management and streamlines application performance.

Figure 2. Platform Block Properties

The Platform Setup tab in Vivado displays the SP tag information associated with each NoC IPs.

Figure 3. SP Tags in Platform Setup

Accessing Memories in Vitis

To facilitate memory access in Vitis, the linker needs connectivity information to establish connection with the LPPDR memories. As mentioned previously, memory selection is accomplished using unique sptags. For designs involving LPPDR memory access, the input/output AXI ports must be connected to a specific tag using a Vitis connectivity file (system.cfg) as shown below. This file is passed to v++ --link command.

[connectivity]
sp=ai_engine_0.M00_AXI:LPDDR
sp=ai_engine_0.M01_AXI:LPDDR

v++ --link --platform <platform_path> <libadf.a> <kernel.xo> --config <system.cfg>

Leveraging the hierarchical memory setup in the platform design in Vivado, Vitis provides access to multiple memory configurations, catering to diverse application requirements:

1. To access all available memory space: use the sptag for the aggr_noc IP. This grants access to all memories connected to the aggr_noc, encompassing NoC_C0_C1,NoC_C2, NoC_C3 and NoC_C4.

   [connectivity]
   sp=ai_engine_0.M00_AXI:LPDDR
   sp=ai_engine_0.M01_AXI:LPDDR

2. Accessing Individual Memories:
   1. Accessing NoC_C0_C1 only

      Utilize the sptag LPDDR01 within the Vitis connectivity file to access only NoC_C0_C1

      [connectivity]
      sp=ai_engine_0.M00_AXI:LPDDR01
      sp=ai_engine_0.M01_AXI:LPDDR01

   2. Accessing NoC_C2 only

      [connectivity]
      sp=ai_engine_0.M00_AXI:LPDDR2
      sp=ai_engine_0.M01_AXI:LPDDR2

   3. Accessing NoC_C3 only

      [connectivity]
      sp=ai_engine_0.M00_AXI:LPDDR3
      sp=ai_engine_0.M01_AXI:LPDDR3

   4. Accessing NoC_C4 only

      [connectivity]
      sp=ai_engine_0.M00_AXI:LPDDR4
      sp=ai_engine_0.M01_AXI:LPDDR4

For AI Engine designs, AIE GMIOs connect to access LPDDR using similar connectivity file as mentioned above.

For instance, for GMIOs (gmio_i_0, gmio_o_0 and gmio_i_1, gmio_o_1) placed on the respective interface tile, the following connectivity options can be used.

Figure 4. Array View

Accessing LPDDR using aggreg_noc::

[connectivity]
sp=ai_engine_0.gmio_i_o_gmio_o_0:LPDDR
sp=ai_engine_0.gmio_i_1_gmio_o_1:LPDDR

Accessing NoC_C2 individually:
[connectivity]
sp=ai_engine_0.gmio_i_o_gmio_o_0:LPDDR2
sp=ai_engine_0.gmio_i_1_gmio_o_1:LPDDR2

It is crucial to modify the system device tree (user-system.dtsi) to reflect any changes in the NoC memory configuration. This ensures the reserved memory space is accurately reflected in the device tree. For details, refer to the custom platform creation tutorial.