Identifying Platform Clocks - 2025.1 English

Identifying Platform Clocks - 2025.1 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID

UG1701

Release Date

2025-07-16

Version

2025.1 English

The kernels can have any number of independent and edge-aligned clocks, and platforms can have multiple kernels running at different clock frequencies under user control. Platforms have a variety of clocking: processor, PL, and AI Engine clocking. The following table explains the clocking for each type.

Table 1. Platform Clocks
Clock	Description
AI Engine	Can be configured in the platform in the AI Engine IP. The AI Engine PLL frequency must match the CIPS HSM0 frequency.
Processor	Can be configured in the platform in the CIPS IP. The HSM0 frequency must match the AI Engine IP PLL frequency.
Programmable Logic (PL)	Can have multiple clocks and can be configured in the platform.
NoC	Device dependent and can be configured in the platform in the CIPS and NoC IP.
These clocks are derived from the platform and are affected by the device, speed grade, and operating voltage.

Vitis clocking automation differentiates between three types of platform clock: scalable, fixed, and fixed_non_ref, which are specified in Vivado during platform capture, and define how automation can employ clocks to meet v++ clocking directives.

Tip: You cannot mix fixed and scalable clocks on a single kernel, but they can be mixed across different kernels within a single .xclbin file.

You can determine the clocks available in the target platform by using the platforminfo command.

=================
Clock Information
=================
  Default Clock Index: 2
  Default Clock Frequency: 312.499712
  Default Clock Pretty Name: PL 2
  Clock Index:         0
    Frequency:         156.249856
    Status:            fixed
    Name:              clk_wizard_0_clk_out2
    Pretty Name:       PL 0
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            6.400006
    Normalized Period: .006400
  Clock Index:         1
    Frequency:         104.166570
    Status:            fixed
    Name:              clk_wizard_0_clk_out1
    Pretty Name:       PL 1
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            9.600009
    Normalized Period: .009600
  Clock Index:         2
    Frequency:         312.499712
    Status:            fixed
    Name:              clk_wizard_0_clk_out3
    Pretty Name:       PL 2
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            3.200003
    Normalized Period: .003200
  Clock Index:         3
    Frequency:         78.124928
    Status:            fixed
    Name:              clk_wizard_0_clk_out4
    Pretty Name:       PL 3
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            12.800012
    Normalized Period: .012800
  Clock Index:         4
    Frequency:         208.333141
    Status:            fixed
    Name:              clk_wizard_0_clk_out5
    Pretty Name:       PL 4
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            4.800004
    Normalized Period: .004800
  Clock Index:         5
    Frequency:         416.666283
    Status:            fixed
    Name:              clk_wizard_0_clk_out6
    Pretty Name:       PL 5
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            2.400002
    Normalized Period: .002400
  Clock Index:         6
    Frequency:         624.999425
    Status:            fixed
    Name:              clk_wizard_0_clk_out7
    Pretty Name:       PL 6
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            1.600001
    Normalized Period: .001600

For Versal devices, the --part option can be used instead of --platform with the v++ --link and v++ --package commands. With --part the tool generates a base design for use on the device, and can generally be used while waiting for the development of a full platform specification. However, the v++ linker generated base platform design employs PLRAM only, so is unsuitable for running Linux applications on the target.

Fixed Clocks

Platform clocks declared as 'fixed' can be used to drive kernels at their specified frequency, or as a reference clock for v++ clock automation to derive clocks as needed.

Fixed clocks use MMCMs to generate frequencies other than the fixed frequencies defined on the platform. For example, if you specify clock frequencies: 60, 200, and 450, the Vitis compiler adds all the necessary logic to generate the required clocks from the available platform fixed clocks.

Use the --freqhz option to specify the clock frequency for a kernel. The --clock Options can also be used to specify PL kernel connections to specific platform clocks, or to specify clock frequencies that are generated from fixed clocks on the platform.

fixed_non_ref

Platform clocks declared as fixed_non_ref can be used to drive kernels at their specified frequency, but cannot be used as a reference clock by v++ clock automation.

The canonical justification for declaring a platform clock fixed_non_ref is because it is driven by an MBUFG logical clock resource.

Refer to --clock Options for more details.

Tip: You cannot mix fixed and scalable clocks on a single kernel, but they can be mixed across different kernels within a single .xclbin file.

You can determine the clocks available in the target platform by using the platforminfo command.

=================
Clock Information
=================
  Default Clock Index: 2
  Default Clock Frequency: 312.499712
  Default Clock Pretty Name: PL 2
  Clock Index:         0
    Frequency:         156.249856
    Status:            fixed
    Name:              clk_wizard_0_clk_out2
    Pretty Name:       PL 0
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            6.400006
    Normalized Period: .006400
  Clock Index:         1
    Frequency:         104.166570
    Status:            fixed
    Name:              clk_wizard_0_clk_out1
    Pretty Name:       PL 1
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            9.600009
    Normalized Period: .009600
  Clock Index:         2
    Frequency:         312.499712
    Status:            fixed
    Name:              clk_wizard_0_clk_out3
    Pretty Name:       PL 2
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            3.200003
    Normalized Period: .003200
  Clock Index:         3
    Frequency:         78.124928
    Status:            fixed
    Name:              clk_wizard_0_clk_out4
    Pretty Name:       PL 3
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            12.800012
    Normalized Period: .012800
  Clock Index:         4
    Frequency:         208.333141
    Status:            fixed
    Name:              clk_wizard_0_clk_out5
    Pretty Name:       PL 4
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            4.800004
    Normalized Period: .004800
  Clock Index:         5
    Frequency:         416.666283
    Status:            fixed
    Name:              clk_wizard_0_clk_out6
    Pretty Name:       PL 5
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            2.400002
    Normalized Period: .002400
  Clock Index:         6
    Frequency:         624.999425
    Status:            fixed
    Name:              clk_wizard_0_clk_out7
    Pretty Name:       PL 6
    Inst Ref:          clk_wizard_0
    Comp Ref:          clk_wizard
    Period:            1.600001
    Normalized Period: .001600