Extensible Hardware Platforms - 2025.1 English - UG1701

Hardware platforms are encapsulated in an extensible XSA that encompasses a Vivado project containing a block design (BD) in which Vitis tools operate. Vivado supports two types of extensible XSAs.

• Flat: Simplest design style, consisting of a single block design representing the top-level module.
• DFX (Dynamic Function eXchange): A block design container (BDC) based platform where the Vitis region BDC has been tagged with the HD.RECONFIGURABLE property (see DFX Based Hardware Platform for details).

It is recommended to follow specific guidelines when building hardware platforms in Vivado:

• IP Restrictions:

  • All IPs used in the platform design must be local to the Vivado Design Suite project. External IP repository references are not supported for extensible XSA creation.
  • Processing subsystem requirement: Include a CIPS (Control Interfaces and Processing System) IP for Versal adaptive SoC, or Processing System for AMD Zynq™ UltraScale+™ MPSoC, or Zynq 7000 SoC. Because processing system IPs have complex configuration, it is recommended to start from an IP instance provided as part of an AMD-verified Configurable Example Design (CED).
  • MicroBlaze Restrictions: Avoid using MicroBlaze processors for controlling PL kernels, except for UltraScale FPGAs.

• Platform Interface Requirements (for more details, see Adding Hardware Interfaces):

  • Platform interface declarations have implied system semantics as follows:

    • AXI4 slave interfaces represent memory apertures
    • AXI4/AXI4-Lite master interfaces represent control bus
    • AXI4-Stream masters and slaves represent data sources and sinks
  • Interrupt
  • Clock
  • Reset

• Clock Pin Requirements for a Platform IP:

  • Any platform IP with an AXI interface used by the Vitis linker to link to PL kernels and AI Engine graphs must also have associated clock pins. This enables v++ to accurately infer and insert clock domain crossing logic when necessary.

• Undeclared bus interfaces and signals

  • The v++ linker supports blind connectivity for non-AXI, non-AXI4-Stream bus interfaces and signals, but such use is atypical. Refer to the Linking the System for further details.

• Project Source File Requirement:

  • All source files for all elements of the Vivado project must be local to the project before exporting it as an XSA. Failing to do so can result in errors when using the platform in the Vitis development flow.

• Building an extensible platform:

  • Ensure the project type is set as Extensible Vitis Platform within the Project Manager Settings or via set_property platform.extensible true [current_project] (Tcl command).