Enabling Hardware Emulation - 2025.1 English - UG1701

The following steps enable hardware emulation in extensible hardware platform.

1. Start with your extensible hardware Vivado project with the BD, RTL, test bench, and other sources. This project can be a flat, or DFX based hardware design.
   1. Configure the AI Engine block with only one slave AXI4 Memory-Mapped port connected to NoC. Vitis linker automatically connects the AI Engine Graph interface to the platform.
2. Update the design to include the right simulation models.
   1. For Versal adaptive SoCs only, prepare the platform design to enable SystemC models. Update the CIPS and NoC IP SELECTED_SIM_MODEL property to TLM. This ensures that for CIPS IP, the design uses QEMU model on which host application runs. Similarly, for Zynq 7000 and Zynq UltraScale+ MPSoCs, set the SELECTED_SIM_MODEL on the processing system IP instance. Following Tcl command can be used in the design. Also, set the parameter to enable SystemC simulation in Vivado:

      foreach tlmCell [get_bd_cells * -hierarchical -filter {VLNV =~ "*:*:axi_noc:*" || VLNV =~ "*:*:versal_cips:*"}] {set_property SELECTED_SIM_MODEL tlm $tlmCell }
      set_param bd.generateHybridSystemC true

3. Ensure the test bench is setup correctly.
   1. Create a test bench in the sim_1 fileset that instantiates the <top> module of your design.
   2. Your test bench should include a BD wrapper instead of the BD directly. This is because the Vitis hardware emulator uses BD wrappers to insert NoC elements during simulation.
   3. For Versal adaptive SoCs, use the launch_simulation -scripts_only command to generate a file called <top>_sim_wrapper.v. This file is a wrapper module that instantiates additional simulation models related to the aggregated NoC.
   4. The following Tcl commands generates the necessary NoC simulation files and can be used in your simulation sources.
   5. Ensure the top synthesis module is also set as the top for simulation in the sim_1 fileset.

      # Ensure that your top of synthesis module is also set as top for simulation
      
      set_property top <rtl_top> [get_filesets sim_1]
      
      # Generate simulation top for your entire design which would include
      # aggregated NOC in the form of xlnoc.bd
      
      launch_simulation -scripts_only
      update_compile_order -fileset sim_1
      
      # Set the auto-generated <rtl_top>_sim_wrapper as the sim top
      
      set_property top <rtl_top>_sim_wrapper [get_filesets sim_1]
      update_compile_order -fileset sim_1
      
      #Generate the final simulation script which will compile
      # the <syn_top>_sim_wrapper and xlnoc.bd modules also
      launch_simulation -scripts_only
      launch_simulation -step compile
      launch_simulation -step elaborate

   6. Compile the design and start simulation. The design is configured to use QEMU, so the CIPS IP does not generate transactions because there is no software present while simulating in the Vivado simulator. The following ERROR message is observed during Vivado simulation, but this indicates that the basic design has loaded correctly.

      ##############################################################
      #
       #  Simulation does not work as Versal CIPS Emulation (SELECTED_SIM_MODLE=tlm) only works with Vitis tool(launch_emulator.py tool in Vitis)
      #
      ##############################################################
       
      ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.

      Note: To confirm that the design generates the right transactions, you can simulate the design using the CIPS VIP. Ensure the SELECTED_SIM_MODEL property is set to RTL for the NoC and CIPS IP. Also, create a test bench that drives the CIPS VIP and meets the requirement of the NoC Verilog model. Refer to the CIPS VIP and NoC IP documentation for additional details on how to set up test bench for Verilog-based simulation.
4. Package the HW Emulation only XSA.
   1. Package the HW Emulation only XSA. Ensure that all source files are local to the project before exporting it. Use the Vivado File > Export > Export Platform option or the following Tcl command to do this:

      set_property platform.platform_state "pre_synth" [current_project]
      write_hw_platform -hw_emu -file  platform_hw_emu.xsa

   2. This XSA can be used with pre-built Linux images or with PetaLinux to create a custom Linux image.