Building and Running the System - 2025.1 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)
Document ID
UG1701
Release Date
2025-07-16
Version
2025.1 English

The AMD Vitis™ tool simplifies hardware design and integration with a software-like compilation and linking flow, integrating the four domains of the AMD Versal™ device: the AI Engine array, the programmable logic (PL) region, the network-on-chip (NoC) and the processing system (PS). The Vitis linker flow lets you integrate your compiled AI Engine design graphs (libadf.a) with additional kernels implemented in the PL region of the device, including HLS and RTL kernels, and link them for use on a target platform. The Vitis linker provides abstract directives for accessing system memory, CPU control, and streaming I/O, so it is often possible to develop AI Engine graphs and kernels on a standard development platform and quickly re-target the AI Engine code to a custom platform developed for your specific application. You can control AI Engine graphs and PL kernels from code running on an embedded Arm® processor on the Versal device or from an external CPU.

The following figure shows the high-level steps required to use the Vitis tools flow to integrate your application. The command-line process to run this flow is described here.
Note: You can also use this flow from within the Vitis IDE as explained in Launching Vitis Unified IDE in the Vitis Reference Guide (UG1702).
Figure 1. Vitis Integrated Flow

Note: Running the application is either on hardware or in emulator.
Important: Using Vitis tools and AI Engine tools require the setup described in Setting Up the Vitis Environment.

The following steps can be adapted to any Vitis project targeting a Versal device.

  1. AMD provides Pre-built Base Platforms for select devices and recommends using the Vitis Integrated Flow. Pre-built embedded base platforms installed with the Vitis installer can be targeted for the design flow or a Custom Platform created can be targeted for the design flow.
  2. As described in Compiling an AI Engine Graph Application in the AI Engine Tools and Flows User Guide (UG1076), the first step is to create and compile the AI Engine graph into a libadf.a file using the AI Engine compiler. You can iterate between the AI Engine compiler and the AI Engine simulator to develop the graph until you are ready to proceed.
  3. PL Kernel Compilation: PL kernels are compiled for implementation in the PL region of the target platform using the v++ --mode hls command, see HLS Kernel Development. In addition to Vitis compilation, you can use Vivado to package RTL modules as kernels in the compiled .xo format as described in Packaging the RTL Code as a Vitis XO. See v++ Mode HLS in the Vitis Reference Guide (UG1702).
  4. Linking the System: Link the compiled AI Engine graph with the HLS kernels and RTL kernels onto a target platform. The process creates an XSA file to encapsulate the implemented hardware system to create boot and loadable images.
  5. PS application compilation: Optionally compile a host application to run on the Cortex®-A72 core processor using the GNU Arm cross-compiler to create an ELF file. The host program interacts with the AI Engine kernels and kernels in the PL region. This compilation step is optional because there are several ways to deploy and interact with the AI Engine kernels, and the host program running on the PS is one way. For more details, see Host Application Development.
  6. Packaging for Vitis Flow: Use the v++ --package process to gather the required files to configure and boot the system, to load and run the application, including the AI Engine graph and PL kernels. The packager can also be invoked to build the necessary package to run emulation and debug, or run your application on hardware.