The MMI file is an XML file that syntactically describes how individual block
RAMs make up a contiguous logical data space. You can create an MMI file from an open
implemented design in the Vivado Design Suite using the write_mem_info Tcl command. The implemented design provides the
needed placement information of the block RAM resources.
UpdateMEM uses the MMI file as input to direct the translation of data into the proper initialization form. The Example MMI file below shows the XML-based syntax used to describe the organization of block RAM usage.
<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="9">
<Processor Endianness="Little" InstPath="design_1_i/microblaze_0">
<AddressSpace Name="microblaze_0_local_memory/dlmb_bram_if_cntlr" Begin="0" End="16384">
<!-- AddressSpaceRange was added to support heterogeneous memories -->
<!-- CoreMemory_Width value should be 32 for RAMB36, 16 for RAMB18 and 256 for URAM288 -->
<AddressSpaceRange Name="microblaze_0_local_memory/dlmb_bram_if_cntlr" Begin="0" End="16384" CoreMemory_Width="32" >
<BusBlock>
<BitLane MemType="RAMB36" Placement="X2Y20" >
<DataWidth MSB="7" LSB="0"/>
<AddressRange Begin="0" End="4095"/>
<BitLayout pattern="p0_d8"/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y18">
<DataWidth MSB="15" LSB="8"/>
<AddressRange Begin="0" End="4095"/>
<BitLayout pattern="p0_d8"/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y17">
<DataWidth MSB="23" LSB="16"/>
<AddressRange Begin="0" End="4095"/>
<BitLayout pattern="p0_d8"/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y19">
<DataWidth MSB="31" LSB="24"/>
<AddressRange Begin="0" End="4095"/>
<BitLayout pattern="p0_d8"/>
<Parity ON="false" NumBits="0"/>
</BitLane>
</BusBlock>
</AddressSpaceRange>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xcvc2802-vsvh1760-2MP-e-S"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfo>