The AMD Vitis™ Networking P4 Tool default interfaces are shown in the following figure and described in the following table.
Figure 1. Vitis Networking P4 Tool Interface
| Name | I/O | Description |
|---|---|---|
| s_axis | I/O | Slave AXI4-Stream interface carrying input packet data. Data bus width is configurable. Details can be found in s_axis Interface. |
| s_axi | I/O | AXI4-Lite bus interface from the Control Plane, used for register access. |
| s_axis_aclk | I | Slave AXI4-Stream clock. |
| s_axis_aresetn | I | Active Low slave AXI4-Stream reset. |
| cam_mem_aclk | I | CAM memory clock. |
| cam_mem_aresetn | I | Unconnected. |
| s_axi_aclk | I | AXI4-Lite clock. |
| s_axi_aresetn | I | Active Low AXI4-Lite reset. |
| m_axi_hbm_aclk | I | Master AXI4-Stream clock. |
| m_axi_hbm_aresetn | I | Active Low HBM reset. |
| m_axi_ddr_aclk | I | Master AXI4-Stream clock |
| m_axi_ddr_aresetn | I | Active Low DDR reset. |
| user_metadata_in | I | Input user metadata bus. Bus width varies depending on the P4 program selected. |
| user_metadata_in_valid | I | Input user metadata valid. Asserted with first word of the corresponding packet. If not asserted, user_metadata_in is treated as all zeroes for that packet. If the axis_tuser/axis_tid/axis_tdest keywords are used, the user_metadata_in_valid port is ignored and the signal will be auto-generated internally for each packet based on the S_AXIS signals. |
| user_extern_in | I | Data input from user Extern interface(s). This vector is extended, depending on the number of user Extern instances. |
| user_extern_in_valid | I | Data in valid from user Extern interface(s). This vector is extended, depending on the number of user Extern instances (for example, a single valid bit per user Extern interface). |
| user_extern_in_ready | O | Data in ready to user Extern interface(s). This vector is only present if an extern in 'variable latency' mode is found in the p4 file. This vector is extended, depending on the number of User Extern instances. |
| m_axis | I/O | Master AXI4-Stream interface carrying output packet data. Data bus width is configurable. Details can be found in m_axis Interface. |
| m_axi_hbmXX | I/O | Master AXI HBM interface(s), where XX represents the interface number in the range of 0 to 31. |
| m_axi_ddrXX | I/O | Master AXI DDR interface(s), where XX represents the interface number in the range of 0 to 3. |
| user_metadata_out | O | Output user metadata bus. Bus width varies depending on the P4 program selected. |
| user_metadata_out_valid | O | Output user metadata valid. Asserted with first word of the corresponding packet. |
| user_extern_out | O | Data output to user Extern interface(s). This vector is extended, depending on the number of user Extern instances. |
| user_extern_out_valid | O | Data output valid to user Extern interface(s). This vector is extended, depending on the number of user Extern instances (for example, a single valid bit per user Extern interface). |
| user_extern_out_ready | I | Data out ready from user Extern interface(s). This vector is only present if an extern in 'variable latency' mode is found in the p4 file. This vector is extended, depending on the number of User Extern instances. |
| irq | O | Interrupt signal asserted when any internal ECC interrupts from BRAM/URAM (CAMs or FIFOs) are triggered. Active High on rising-edge of s_axis_clk domain. |