The following are the reset signals used in the Vitis Networking P4 IP:
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s_axis_aresetn - Active-Low slave AXI4-Stream reset.
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s_axi_aresetn - Active-Low AXI4-Lite reset. It resets the AXI4-Lite interface signaling but it does not reset any of the register maps (such as Statistics Registers and table entries).
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m_axi_hbm_aresetn - Active-Low HBM reset. This is the DRAM memory interface reset. It resets all FSMs that manage memory access, pending and uncompleted memory transactions.