Register Extern - 2025.1 English - UG1308

The architecture-specific implementation of the Register Extern closely follows the PSA/PNA specification. It provides a mechanism for keeping stateful memories, whose values can be read and written in the data plane. Register Extern values can also be read and written from the control plane.

This extern is limited to:

• Single read and/or write access per packet.
• Widths from 1 to 4096 bits.
• Support for up to 64k registers per instance.
• Support for on-chip memory only.
  • The register values are stored in LUTRAM, block RAM, or URAM, depending on the number of elements.
    Note: ECC is only supported when block RAM or URAM memory type is used.
• Support for atomic read-modify-write operations to a single index per packet.
  • In the case of both read and write access, read must occur first.

In the case of read-modify-write operations, the compiler identifies the action located in between and generates the RTL accordingly to achieve maximum performance. The following limitations apply:

• A maximum latency of four clock cycles is supported. It is important to code as efficiently as possible to be able to achieve maximum performance. Higher latencies lead to lower performance.
• Continuous access to the same index might result in lower performance due to its atomic behavior.
• Actions are allowed in between register reads/writes only if they do not exceed the maximum allowed modify operation latency.

See Register Map in Chapter 4 for the Register Extern register map.

The Register Extern is defined in xsa.p4 as:

extern Register<T, S>{
    Register(bit<32> size);
    void read(in S index, out T result);
    void write(in S index, in T value);
}

An example of a Register Extern being used in an example P4 program can be seen in the TCP Example Design (see Tcp_fsm Example Design).