Facts about AMD LogiCORE™ IP associated with AMD Vitis™ Networking P4 are as follows:
| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 | AMD UltraScale™ , AMD UltraScale+™ , AMD Versal™ |
| Supported User Interfaces | AXI4-Stream and AXI4-Lite Interfaces 2 |
| Provided with Core | |
| Design Files | Encrypted Verilog RTL |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx Design Constraint (XDC) |
| Simulation Model | P4BM C++ Behavioral Model |
| Supported S/W Driver 3 | Standalone |
| Software Example Design Application | Standalone, AMD Vivado™ IP integrator |
| Tested Design Flows 4 | |
| Design Entry 5 | Standalone, Vivado IP integrator |
| Simulation 6 | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: N/A |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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