HBM/DDR BCAM (EM) - 2025.1 English - UG1308

HBM/DDR BCAM (EM - exact match) is a binary match of a search key to one of the keys stored within the table, inside the HBM/DDR memory. HBM/DDR allows for significantly larger tables to be supported compared to URAM/BRAM-based tables. The associated value for the key is returned within the response as well as an indication of whether the key produced a match. This CAM type is only supported on a Versal™ device. Multiple instances of HBM/DDR BCAM are supported, including HBM and DDR combined within the same P4 instance. The required RAM size for each instance (RamSizeKBytes) can be found in the generated <design_name>_pkg.sv file (see Generated Files) and is also displayed on the GUI Tables tab under Memory Resources.

• Key width: 10 to 992 bits.
• Response width: 1 to 1006 bits.
• Look-up rate is dependent on many factors, including if a cache is enabled and what the cache hit rate is.
• Size: 8192 to 60 million entries.
• Hit/miss flag: Yes.

The following is an example of how to instantiate a HBM/DDR BCAM in a P4 file:

    table forwardIPv4 {
        key             = { hdr.ipv4.src : exact;
                            hdr.ipv4.dst : exact; }
        actions         = { forwardPacket; 
                            dropPacket; } 
        size            = 1048576;
        default_action  = dropPacket;
    }

The following block diagram shows a Vitis Networking P4 IP with a DDR BCAM instance.

Figure 1. Vitis Networking P4 IP with DDR BCAM

The following block diagram shows a Vitis Networking P4 IP with a HBM BCAM instance.

Figure 2. Vitis Networking P4 IP with HBM BCAM

For more detailed information on how the compiler selects a BCAM, see Compiler Table Selection. You must also select a 'High Bandwidth RAM' or 'DDR' style in the Vitis Networking P4 GUI (see Example Design Use (with HBM/DDR BCAM)). For more information on HBM/DDR BCAMs, see Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427).