Guidelines for Porting P4 Code to the AMD Architecture - 2025.1 English - UG1308

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Release Date
2025-05-29
Version
2025.1 English

There are some architecture-specific changes required when porting P4 code from other targets. Here is an example to show the changes required when porting P4 code from the V1Switch architecture:

  • Replace the included architecture file:
    • #include <v1model.p4> should be replaced with #include <xsa.p4>
  • The Vitis Networking P4 Architecture has only three components: Parser, Match-Action, and Deparser. A P4 program needs to be modified to fit into this architecture. For example, moving from V1Model to XSA:
    • V1Switch should be renamed to XilinxPipeline.
    • VerifyChecksum and ComputeChecksum must be removed as these controls are not supported in XSA.
    • Ingress and Egress pipelines must be combined into one Match-Action pipeline.
  • Deparser control has metadata and standard_metadata_t inouts, similar to the Parser and Match-Action pipelines. These must be added to the Deparser control declaration (even if they are not used in the P4 program).
  • The standard metadata structure is different and only has a few fields. Any use of other standard metadata fields from the V1Model must be removed, or replaced with user metadata.
  • Supported externs are different in XSA compared to the V1Model. Check the latest XSA to see which externs are supported and the syntax involved.