Example Design Use (with HBM/DDR BCAM) - 2025.1 English - UG1308

Vitis Networking P4 User Guide (UG1308)
Document ID
UG1308
Release Date
2025-05-29
Version
2025.1 English

The steps to run the FiveTuple example design using HBM BCAM with the Questa simulator are as follows:

  1. Open a Vivado project and select a device that has HBM DRAM.
  2. Instantiate the Vitis Networking P4 IP: Click IP Catalog, then double-click Vitis Networking P4.
  3. Select a P4 file from the FiveTuple directory <Vivado_install_area>/data/ip/xilinx/vitis_net_p4_v2_3/example_design/examples/five_tuple.
  4. In the Tables tab drop-down menu under Ram Style, select HBM. The Memory Resources entry updates to show the number of HBM pseudo channels used.
  5. Right-click vitis_net_p4_0 in the Sources window and click Open IP Example Design.
  6. In the new Example Design Vivado project, change the target simulator: Click Settings under PROJECT MANAGER in the panel on the left, select Simulation under Project Settings, and select the target simulator you want to use.
  7. Verify that the compiled library location is set correctly to point to the correct pre-compiled simulation libraries. See the Vivado Design Suite User Guide: Logic Simulation (UG900) for instructions on how to compile simulation libraries.
  8. Click Run Simulation under Simulation in the panel on the left. This launches the Questa simulator.
  9. The simulation is run for a maximum of 10 us.
Note: To run this example design simulation using VCS simulator, select the Verilog Compiler simulator (VCS) instead of the Questa simulator.
Note: To run this example design simulation using DDR instead of HBM, in step 4, select 'DDR' instead of 'HBM'.
Note: If running HBM example designs using the Questa simulator, the following property needs to be set: set_property -name {questa.elaborate.vopt.more_options} -value {-inlineFactor=0} -objects [get_filesets sim_1]