ECC is supported and enabled on the logic CAMs by default and cannot be
disabled. ECC is disabled by default on Direct Tables, Counter Externs and re-alignment
FIFOs but you can choose to enable it by selecting the associated box. This only applies
where these are implemented in Block RAM or URAM, ECC for LUTRAM is not supported. Any
single-bit ECC errors are detected and corrected when data is read from the RAMs.
Double-bit ECC errors are detected but cannot be automatically corrected. ECC errors are
flagged to software via an interrupt port irq (see Vitis Networking P4 Tool Interface). The Statistics register, if enabled, includes ECC
debug/status registers (see Register Map).
There are also ECC error-scrubbing mechanisms included to read all entries of the BRAMs and URAMs every 1 ms for early detection of ECC errors. In case of single-bit error detection, the corrected data is then automatically written back to the RAM to remove the error.