For the DPI library to be able to trigger the execution of a SystemVerilog task, the interface to the task must be known to the DPI library. In practice, this means that it must be hard-coded in both the SystemVerilog test bench and the DPI library.
For the example designs, two tasks called axi_lite_wr and axi_lite_rd (located in
example_control.sv) are defined and can be called from the DPI library. These tasks
contain the logic needed to issue writes and reads to the AMD Vitis™
Networking P4 IP's AXI interface. The axi_lite_wr task takes two integer inputs (address and data), the axi_lite_rd task takes one integer input (address) and one
integer output (data). You are encouraged to develop your own custom test bench. The DPI
library provided with Vitis Networking P4 can be used in any such test bench, provided
that the test bench defines these two tasks as described in this section.