Segmented Configuration is a solution that enables you to boot the processors in a Versal device and access DDR memory before the programmable logic (PL) is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can be configured later if needed via any primary or secondary boot device or through a DDR image store. The Segmented Configuration feature is intended to present the Versal boot sequence with similar flexibility to configure PL as can be done with Zynq UltraScale+ MPSoCs.
This solution uses a standard Vivado
tool flow through implementation with the only additional annotation required being the
identification of NoC path segments included in the initial boot image. This occurs
automatically after the project property enabling the feature has been set. Programming
image generation (write_device_image) automatically
splits the programming images into two PDI files to be stored and delivered separately.
The entire PL is dynamic and can be completely reloaded while any operating system and
DDR memory access remain active.
For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 architectures, Segmented Configuration is the only methodology presented – all programming images are generated in two parts so you can boot the processing system independent of the programmable logic. Additional documentation is provided to clearly declare the resources and features that are available after the initial boot of the device. This requires the PL to reach full functionality. Mechanisms to stitch the two images into a single monolithic image (with discrete segmented events within) are available.
For more information on Segmented Configuration, including design requirements and a tutorial walk-through, see the Segmented Configuration tutorial available from the AMD Vivado GitHub repository.