PS Wizard - 2025.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2025-05-29
Version
2025.1 English

For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, the processing system (PS), PMC, and ASU modules are grouped together and configured using the Processing System Wizard IP core as shown in the following figure. For more information on the PS Wizard, see the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Processing System Wizard IP Product Guide (PG450). For more information on the power domains, see the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).

Note: Not all devices in the Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 have 8x A78AEs and 10x R52s. Additionally, for the 2VM3654 device in the Versal Prime Series Gen 2, cache, cluster configuration, and other details may vary from the content below. For more detail and device-specific information, see the Versal Architecture and Product Data Sheet: Overview (DS950).
Figure 1. Device-Level Interconnect Architecture for Versal Devices