Multiplexed I/O - 2025.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2025-05-29
Version
2025.1 English

The Versal adaptive SoC multiplexed I/O (MIO) are similar to the MIO on the Zynq UltraScale+ MPSoCs. In Versal devices, there are 78 MIO pins, 52 signals in the PMC MIO (banks 500 and 501), and 26 signals in the LPD MIO (bank 502). For details on MIO pin planning, see this link and this link in the Versal Adaptive SoC Technical Reference Manual (AM011). For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, see the Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026). The Versal adaptive SoC CIPS/PS Wizard IP is used to select the MIOs to use and specify their functionality.