Important: The CIPS
IP is applicable to most devices with the
Arm®
Cortex®-A72-based processing system. The relevant
families are Versal AI Edge Series, Versal AI Core Series, Versal Prime Series, and Versal Premium Series.
The following devices use the PS Wizard IP within Vivado, but have a processing system architecture like what is described in this section: VP1902 and VM2152.
The PS, PMC, and CPM modules are grouped together and configured using the Control, Interface, and Processing System (CIPS) IP core as shown in the following figure.
Note: The Versal adaptive SoC includes multiple power domains. In the PS, the RPU
is in the low-power domain (LPD), the APU is in the full-power domain (FPD), and the
platform management controller (PMC) is in the PMC power domain. There are two
implementations of the CPM depending on the target device capability: CPM4 that is
compliant with the PCI Express Base Specification
Revision 4.0 and CPM5 that is compliant with the PCI Express Base Specification Revision 5.0. CPM4 is fully powered by the
PL domain while CPM5 is powered by its own dedicated supply (VCC_CPM5) as well as the PS
LPD. For more information on the power domains, see the
Versal
Adaptive SoC Technical Reference Manual (AM011).
Figure 1. Device-Level Interconnect Architecture
