CIPS/PS Wizard IP Core - 2025.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2025-05-29
Version
2025.1 English

The CIPS/PS Wizard IP allows you to configure the following:

  • Device clocking to the PMC, PS, NoC, and optionally, PL
  • PMC flash controllers, peripherals, and their associated multiplexed I/O (MIO)
  • PS peripherals and their associated I/O
  • PS-PL interrupts and cross-triggering
  • CPM (the integrated block for PCIe® with DMA and cache coherent interconnect) for CIPS IP
  • PS and CPM AXI interfaces to NoC and PL
  • System Monitor supply and temperature monitoring and alarms
  • HSDP for high-speed debugging

For more information, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352) or Versal AI Edge Series Gen 2 and Prime Series Gen 2 Processing System Wizard IP Product Guide (PG450).