In this tutorial, we demonstrated how to optimize C code for Vitis HLS using Code Analyzer. We presented a case study based on the CRYSTALS-Kyber algorithm, polynomial vectorization, and number-theoretic transforms.
We used the Code Analyzer to glean helpful insights about the algorithm, then applied those insights through actionable code changes.
Finally, we measured the performance impact and observed how the dataflow optimization enabled task-level parallelism to deliver a sizeable performance gain.
The example shown in this tutorial serves as a reference for how these concepts can be used to write high performance IP for AMD FPGAs in a fraction of the time needed compared to a pure RTL flow.
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