Vitis Tutorials: Embedded Software (XD260) - 2025.1 English - Learn about Vitis Embedded Design flows. - XD260

Document ID: XD260
Release Date: 2025-07-31
Version: 2025.1 English

Vitis Embedded Software Tutorials
Getting Started in Vitis Unified Embedded IDE
Get Started
Setup Workspace
Create Platform
Create Application
View Domain settings
Set Up target Connection
Build Application and Deploy on Target
Viewing all Vitis IDE CLI commands
Program Flash
Rebuilding Vitis Workspace from CommandLine
Feature Tutorials
Migrating from classic Vitis IDE to Vitis Unified IDE
Migration Script from Vitis Classic IDE to Vitis Unified IDE
Migration Script Limitations
Metadata transfer Methodology change from Hardware to Software
System Device Tree (SDT)
Lopper
CMake
Domain (BSP) metadata
How is Hardware Metadata passed to baremetal driver
Vitis Classic MDD file
Vitis YAML file
Validating the AXI GPIO in the Domain
How is Metadata passed to baremetal libraries
Library YAML file
Modifiying the Library metadata
Vitis Classic workspace to Unified workspace Migration Demo
Manual Migration
Updating the XSA
Vitis Classic to Unified Migration Utility
Summary
Vitis Embedded Scripting Flow
Building Demo XSA file
Launching Vitis CommandLine Interface (CLI)
Component creation using the Vitis commands
Create Vitis Client
Client Help
Create Vitis workspace
Create Vitis Platform
Opening an existing Vitis Platform
Add Software Repository
List/get Vitis domains in a Platform
Create Vitis domains in a Platform
Update hardware in existing Vitis Platform
Building Platform
View or Manipulate Vitis Domains
get_os
get_drivers
get_libs
Library/driver parameters
get_config
set_config
Getting Compiler option on Domain
Setting Compiler option on Domain
Get list of Embedded Application Templates
Creating Vitis Application
Setting Application Compiler option
Building Vitis Application
Metadata extraction using HSI API
Import HSI Python Package
Import XSA file
Close Hardware Design
Get System Info from XSA
Get all IP in XSA
Get cell properties
Get all IP in Address Map of Processor
Get Pins on an IP
Get Interface Pins on an IP
Deploy and Debug firmware using XSDB Python API
Import xsdb python package
Start a session
XSDB Help
Connect to a hw_server
Connect to GDB
Get all JTAG Targets
Get all Targets
Filter on a specific Target
Dowload ELF to target
Dowload PDI to Versal target
Dowload Data file to target
Launching jtagterminal
Memory read/write
Program Hello World ELF onto Zynq Ultrascale+
Program PDI onto Versal
Using example script
User Managed Mode in Vitis Unified IDE
Use Case 1 - Regenerate a previously created Vitis Unified Workspace using a Python Script
Let’s get started
Generating Build Configuration
Running a Build Configuration
Deploying the application on the target
Use Case 2 - Running Platform Creation tutorials
Lets get started
Generating Build Configuration
Running a Build Configuration
Use Case 3 - Generate and deploy u-boot from Git sources
Lets get started
Creating a Build Configuration
Running a Build Configuration
Running a Clean Configuration
Sharing Build Configurations.
Summary
Vitis Embedded Software Debugging Guide
Debugging Bare-Metal Applications
Getting Started
Example Design
Build Instructions
Build XSA
Build Vitis Unified Workspace
Error 1: Error Launching Program
Error 2: Unfinished DMA Operation
Error 3: Unexpected DMA Transfer Result
Error 4: Assertion
Error 5: Non-Lowercased Characters
Debugging Linux Applications
Getting Started
Error 1: Failed in Validating the test connection
Setting Up the Ethernet Connection
Connecting to Physical Board
Connecting to QEMU
Setting Up the TCF Agent
Physical Board Linux Agent
QEMU Linux Agent
Error 2: Multithread Application Debug
Error 3 : Dynamic Memory Allocation
Appendix
Vivado Design
Creating the Block Design
Generating the Bitstream
Exporting the XSA
Automation Steps
PetaLinux Build
Creating a Debuggable First Stage Boot Loader
Where is the FSBL built
Enabling Detailed Prints in FSBL in Vitis Unified IDE
Modifying the FSBL BSP
Building the Project
Debugging FSBL Using the Vitis Debugger
Creating and Modifying FSBL in Vitis Unified IDE
Disabling Optimizations
Cross Triggering in Vitis Unified Embedded IDE
Building the HW
Processor to Processor Cross Triggering
Setup Cross Triggering in Launch Configuration
PL to Processor Cross Triggering
Processor to PL Cross Triggering
Summary

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