The MicroBlaze system includes native AMD IP including:
MicroBlaze processor
AXI block RAM
Double Data Rate 3 (DDR3) memory
UARTLite
AXI GPIO
MicroBlaze Debug Module (MDM)
Proc Sys Reset
Local memory bus (LMB)
Parts of the block design are constructed using the Platform Board Flow feature.
This lab also shows the cross-trigger capability of the MicroBlaze processor.
The feature is demonstrated using a software application code developed in the Vitis software platform in a stand-alone application mode.
This lab targets the AMD SP701 FPGA Evaluation Kit.