Revision History - Revision History - 2024.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
Document_ID
UG909
Release_Date
2024-12-13
Version
2024.2 English

The following table shows the revision history for this document.

Section Revision Summary
12/13/2024 Version 2024.2
Using Visualization Scripts Updated the section.
Defining Netlist Sources Updated the section.
Adding Reconfigurable Module Constraints Updated the section.
Opening Post-synthesis Configurations Created new section.
Automatic Adjustments for PU on Pblocks Updated the section.
Expansion of CONTAIN_ROUTING Area Updated the section.
Reduce the Number of Partition Pins Updated the tip.
Avoid Disjoint Pblocks Whenever Possible for UltraScale and UltraScale+ Devices Updated the last paragraph.
DFX Design Migration from Standard Flow to Advanced Flow Created new section.
Floorplanning Visualization
  • Added a note.
  • Updated the table.
Design Entry Methodology for DFX Designs that use NoC
  • Re-wrote the section, including an update to the title from NoC Topology and Path Ownership in DFX Using NoC IP in IP Integrator.
  • Created new sub-sections.
Avoid Disjoint Pblocks Whenever Possible for Versal Devices Removed references to HDPR 131, 132, and 133, as they have been removed from 2024.2.
Using Report DFX Summary Updated the section.
Design Clock Utilization Summary
  • Added Clock Track to the table.
  • Updated the image.
SLL Summary Created new section.
PPLOC Summary Updated the image.
RP Details
  • Updated the image.
  • Removed text from the Overlap Tiles Count entry in the table.
Shared Tile Reason Created new section.
Using Vivado Debug Cores Added a note.
Segmented Configuration Created new section.
  • INI Strategy
  • 1:N and M:1 NoC Connectivity using INI
 Removed the sections
06/12/2024 Version 2024.1
Creating Pblocks for UltraScale and UltraScale+ Devices Added examples.
Design Elements Inside Reconfigurable Modules Added information on high-speed channelized cryptography engines (HSC).
Floorplanning for Versal Devices Added information on the HSC_TILE tile and updated examples.
NoC Traffic Impact During Reconfiguration Added new section.
Logical Decoupling Added information on timeout for logical decoupling in the NoC.
Using Report DFX Summary Added new section.
Design Version Compatibility Checks Added new section.
Supported Devices Updated devices.