Resolution - Resolution - 2024.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2024-12-19
Version
2024.2 English

Remove the primary clock definition on the hierarchical pin, or if the downstream clock is absolutely needed, use a generated clock constraint with the driver clock specified as master clock instead.