Example - Example - 2024.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document_ID
UG906
Release_Date
2024-12-19
Version
2024.2 English

In the following figure, a LUT is used to gate the clock with a clock enable signal. The LUT on the path can cause excess skew, which is undesirable.

Figure 1. LUT on the Clock Tree
Page-1 Sheet.1 Process Process.7 LUT cell exists on the clock tree LUT cell exists on the clock tree Sheet.4 Sheet.6 X15530-111715 X15530-111715