RETIMING_BACKWARD VHDL Example - RETIMING_BACKWARD VHDL Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document_ID
UG901
Release_Date
2024-12-11
Version
2024.2 English
attribute retiming_backward : integer;
attribute retiming_backward of my_sig : signal is 1;